A Σ-Δ ADC with a DPOQ system and a new multi-Stage digital filter

This paper proposes a high-precision Sigma Delta ADC for automotive electronic sensors and delves into methods for optimizing quantizers and filters, with a focus on DPOQ quantizers and hybrid CIC filters. This ADC features a Dual-path One-bit Quantization (DPOQ) System, which improves the accuracy of Sigma-Delta ADCs while reducing hardware consumption. Meanwhile, this paper presents a new multistage digital filter. The filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC’s accuracy. The filter are designed using canonical signed digit (CSD) and common subexpression (CSE) optimized the design algorithm of the filter, to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 180 nm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, and total power of 518.35 uW.