{"title":"采用折叠正反馈技术的基于 PVT 的 Gm-R 残差放大器","authors":"Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding","doi":"10.1016/j.mejo.2024.106352","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents a process, voltage and temperature (PVT) robust Gm-R-based residue amplifier (RA). The proposed folded positive feedback (FPF) technique facilitates a high open-loop gain of 49.2 dB and gain bandwidth of 30.6<!--> <!-->GHz without employing multiple cascading stages or cascode devices, consuming only 8.2<!--> <!-->mW. The PVT robustness of the proposed RA is self-adapted, addressing the requirement of bias-generating circuitry. Transistor level design and simulations are implemented based on a 28 nm CMOS process. Configured in closed-loop, the proposed RA demonstrates a relative gain variation smaller than 5% and a fast settling time of 400<!--> <!-->ps. The simulated gain linearity exceeds 9<!--> <!-->bit with a 440<!--> <!-->m<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>p</mi><mi>p</mi></mrow></msub></math></span> output swing, yielding an improved trade-off between speed and accuracy in nanoscale RA designs.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique\",\"authors\":\"Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding\",\"doi\":\"10.1016/j.mejo.2024.106352\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper presents a process, voltage and temperature (PVT) robust Gm-R-based residue amplifier (RA). The proposed folded positive feedback (FPF) technique facilitates a high open-loop gain of 49.2 dB and gain bandwidth of 30.6<!--> <!-->GHz without employing multiple cascading stages or cascode devices, consuming only 8.2<!--> <!-->mW. The PVT robustness of the proposed RA is self-adapted, addressing the requirement of bias-generating circuitry. Transistor level design and simulations are implemented based on a 28 nm CMOS process. Configured in closed-loop, the proposed RA demonstrates a relative gain variation smaller than 5% and a fast settling time of 400<!--> <!-->ps. The simulated gain linearity exceeds 9<!--> <!-->bit with a 440<!--> <!-->m<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>p</mi><mi>p</mi></mrow></msub></math></span> output swing, yielding an improved trade-off between speed and accuracy in nanoscale RA designs.</p></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-08-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124000560\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000560","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
摘要
本文介绍了一种基于 Gm-R 的残差放大器(RA),具有工艺、电压和温度(PVT)鲁棒性。所提出的折叠式正反馈 (FPF) 技术无需采用多级级联或级联器件,即可实现 49.2 dB 的高开环增益和 30.6 GHz 的增益带宽,功耗仅为 8.2 mW。拟议 RA 的 PVT 鲁棒性是自适应的,满足了偏置产生电路的要求。晶体管级设计和模拟基于 28 纳米 CMOS 工艺实现。在闭环配置中,拟议的 RA 显示出小于 5% 的相对增益变化和 400 ps 的快速稳定时间。模拟增益线性度超过 9 位,输出摆幅为 440 mVpp,从而改进了纳米级 RA 设计中速度与精度之间的权衡。
A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique
This paper presents a process, voltage and temperature (PVT) robust Gm-R-based residue amplifier (RA). The proposed folded positive feedback (FPF) technique facilitates a high open-loop gain of 49.2 dB and gain bandwidth of 30.6 GHz without employing multiple cascading stages or cascode devices, consuming only 8.2 mW. The PVT robustness of the proposed RA is self-adapted, addressing the requirement of bias-generating circuitry. Transistor level design and simulations are implemented based on a 28 nm CMOS process. Configured in closed-loop, the proposed RA demonstrates a relative gain variation smaller than 5% and a fast settling time of 400 ps. The simulated gain linearity exceeds 9 bit with a 440 m output swing, yielding an improved trade-off between speed and accuracy in nanoscale RA designs.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.