DG-GNR-DMG 垂直隧道场效应晶体管的器件和电路级性能评估

IF 2.7 Q2 PHYSICS, CONDENSED MATTER
Zohming liana , Manas Ranjan Tripathy , Bijit Choudhuri , Brinda Bhowmick
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引用次数: 0

摘要

本作品介绍了基于石墨烯纳米带(GNR)的沟道双栅(DG)双栅材料垂直隧道场效应晶体管(VTFET)与全硅材料隧道场效应晶体管性能的比较研究。由于二维(2D)材料 GNR 具有低带隙、高迁移率和高饱和速率的特性,因此建议将其作为沟道材料,以提高器件性能。我们首次对该器件进行了直流、射频和电路级性能分析。在漏极电压 V = 0.5 V 时,与硅垂直隧道场效应晶体管(36 mV/decade)相比,基于 GNR 的沟道 VTFET 平均阈下摆幅 (SS) 为 16 mV/decade,表现更佳。此外,还研究了温度对直流参数的影响以及这两种结构的模拟/射频 FOM。此外,还将其性能与其他已报道的作品进行了比较;结果表明,DG-GNR-DMG-VTFET 比基于硅(Si)的 VTFET 和其他上述 TFET 作品具有更好的性能。最后,通过为拟议结构设计逆变器和环形振荡器电路,进行了电路级分析,并比较了这两种器件的性能。器件级仿真使用了市场上销售的 Silvaco ATLAS TCAD 仿真器。此外,还使用基于查找表的 Verilog-A 模型在 Cadence Virtuoso 工具中进行了电路级分析。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

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CiteScore
6.50
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