Xiaoning Ma;Qinzhi Xu;Chenghan Wang;He Cao;Jianyun Liu;Daoqing Zhang;Zhiqiang Li
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The equivalent electrical conductivity model is also built up to describe the design features of the redistribution layer (RDL), bump, and through silicon via (TSV) structures based on the electrical-thermal duality. Furthermore, the governing equations for voltage distribution and temperature distribution are solved simultaneously by utilizing the finite volume method (FVM) with nonuniform mesh to realize the electrical-thermal co-simulation of the multiscale CHI system. The model application is further performed to investigate the influence of the model parameters on the voltage drop and temperature distribution of the CHI system. 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引用次数: 0
摘要
芯片异质集成(CHI)是延续摩尔定律的重要技术选择之一。然而,由于 CHI 系统具有高功率、低供电电压的特点,因此需要在功率传输网络(PDN)中流过大电流,焦耳热效应会导致 CHI 系统整体温度升高。同时,高温将导致电流和系统性能下降,并引发一系列可靠性问题。本文提出了一种有效的电热耦合模型,用于预测 2.5-D CHI 系统的稳态温度分布,其中考虑了焦耳热效应和温度对红外压降的影响。还建立了等效电导率模型,以描述基于电热二元性的再分布层 (RDL)、凸块和硅通孔 (TSV) 结构的设计特征。此外,利用非均匀网格有限体积法(FVM)同时求解了电压分布和温度分布的支配方程,实现了多尺度 CHI 系统的电热协同模拟。模型应用进一步研究了模型参数对 CHI 系统压降和温度分布的影响。本研究的验证系统和模拟结果证明了电压场和温度场协同模拟的可行性和准确性,并表明新提出的电热模型有助于对具有焦耳热效应的封装结构进行热分析和压降分析,并可用于辅助 2.5-D CHI 或 3-D 异构堆叠芯片的物理设计优化。
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems
Chiplet heterogeneous integration (CHI) is one of the important technology choices to continue Moore’s law. However, due to the characteristics of high power and low supply voltage in CHI systems, heavy currents need to flow through the power delivery network (PDN), and the Joule heating effect will result in the overall temperature increase of the CHI system. Meanwhile, the high temperature will cause the current as well as the performance of the system to degrade and a series of reliability problems will occur. In this article, an effective electrical-thermal coupling model is proposed to predict the steady-state temperature distribution of a 2.5-D CHI system considering the Joule heating effect and the temperature effect on the IR drop. The equivalent electrical conductivity model is also built up to describe the design features of the redistribution layer (RDL), bump, and through silicon via (TSV) structures based on the electrical-thermal duality. Furthermore, the governing equations for voltage distribution and temperature distribution are solved simultaneously by utilizing the finite volume method (FVM) with nonuniform mesh to realize the electrical-thermal co-simulation of the multiscale CHI system. The model application is further performed to investigate the influence of the model parameters on the voltage drop and temperature distribution of the CHI system. The verified systems and simulated results of the present investigation demonstrate the viability and accuracy of voltage and temperature field co-simulation and indicate that the new proposed electrical-thermal model is helpful in thermal and voltage drop analysis of packaging structures with the Joule heating effect and can be adopted to assist in the physical design optimization of 2.5-D CHI or 3-D heterogeneous stacked chips.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.