Linhong Lu , Xinghua Fu , Rui Hu , Fashun Yang , Jiexin Lin , Zhongchen Bai , Kui Ma
{"title":"嵌入 TTSV 散热阵列的功率芯片的新型精确稳态热阻模型","authors":"Linhong Lu , Xinghua Fu , Rui Hu , Fashun Yang , Jiexin Lin , Zhongchen Bai , Kui Ma","doi":"10.1016/j.mejo.2024.106336","DOIUrl":null,"url":null,"abstract":"<div><p>a novel oblique pyramid equivalent heat dissipation model is proposed for theoretically analyzing heat dissipation capacity of power chips with embedded TTSVs. Extra carefully researching correction of oblique thermal resistance, additional lateral thermal resistance, and thermal resistance of TSV insulation sleeve, the accurate theoretical thermal resistance model was established. Setting the FEA simulating results based on <em>COMSOL Multiphysics</em> as benchmark, heat dissipation effects of variation of radius of TTSV (<em>r</em>), thickness of the power chip (<em>H</em><sub>0</sub>), and side length of the single cell (<em>L</em><sub>0</sub>) have been numerically investigated. The maximum temperature relative error of the proposed model with FEA simulated results is not more than 0.2 %, 1 %, and 0.5 % for variation of <em>r</em>, <em>H</em><sub>0</sub>, and <em>L</em><sub>0</sub>, respectively. The proposed model has been theoretically and numerically proven to be effective and accurate.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Novel accurate steady-state thermal resistance model for power chips embedded in TTSVs heat dissipation array\",\"authors\":\"Linhong Lu , Xinghua Fu , Rui Hu , Fashun Yang , Jiexin Lin , Zhongchen Bai , Kui Ma\",\"doi\":\"10.1016/j.mejo.2024.106336\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>a novel oblique pyramid equivalent heat dissipation model is proposed for theoretically analyzing heat dissipation capacity of power chips with embedded TTSVs. Extra carefully researching correction of oblique thermal resistance, additional lateral thermal resistance, and thermal resistance of TSV insulation sleeve, the accurate theoretical thermal resistance model was established. Setting the FEA simulating results based on <em>COMSOL Multiphysics</em> as benchmark, heat dissipation effects of variation of radius of TTSV (<em>r</em>), thickness of the power chip (<em>H</em><sub>0</sub>), and side length of the single cell (<em>L</em><sub>0</sub>) have been numerically investigated. The maximum temperature relative error of the proposed model with FEA simulated results is not more than 0.2 %, 1 %, and 0.5 % for variation of <em>r</em>, <em>H</em><sub>0</sub>, and <em>L</em><sub>0</sub>, respectively. The proposed model has been theoretically and numerically proven to be effective and accurate.</p></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-07-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239124000407\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000407","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Novel accurate steady-state thermal resistance model for power chips embedded in TTSVs heat dissipation array
a novel oblique pyramid equivalent heat dissipation model is proposed for theoretically analyzing heat dissipation capacity of power chips with embedded TTSVs. Extra carefully researching correction of oblique thermal resistance, additional lateral thermal resistance, and thermal resistance of TSV insulation sleeve, the accurate theoretical thermal resistance model was established. Setting the FEA simulating results based on COMSOL Multiphysics as benchmark, heat dissipation effects of variation of radius of TTSV (r), thickness of the power chip (H0), and side length of the single cell (L0) have been numerically investigated. The maximum temperature relative error of the proposed model with FEA simulated results is not more than 0.2 %, 1 %, and 0.5 % for variation of r, H0, and L0, respectively. The proposed model has been theoretically and numerically proven to be effective and accurate.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.