用于 DNN 的可重构多精度量化感知非线性激活函数硬件模块

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
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引用次数: 0

摘要

近年来,深度神经网络(DNN)中的非线性激活函数(NAF)种类越来越多,导致了更高的计算要求。然而,硬件实现面临着缺乏灵活性、硬件成本高、精度有限等挑战。本文提出了一种高度灵活、低成本的硬件解决方案来实现激活函数,以克服这些问题。我们的方法基于分片线性(PWL)近似方法,通过定制的实现策略支持不同精度配置的 NAF,以满足不同场景应用的要求。本文对激活函数的对称性进行了研究,并结合曲线平移预处理和数据量化技术,以显著降低硬件存储成本。本研究提出的模块化硬件架构支持多种精度的 NAF,适用于设计各种场景下的深度学习神经网络加速器,避免了为激活函数层设计专用硬件电路,提高了电路设计效率。所提出的硬件架构在赛灵思 XC7Z010 开发板上进行了验证。实验结果表明,在 312.5 MHz 的时钟频率下,平均绝对误差 (AAE) 降低了约 35.6%。此外,在 PyTorch 框架下替换 DNN 的激活层函数后,模型的精度损失达到最大值 -0.684%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A reconfigurable multi-precision quantization-aware nonlinear activation function hardware module for DNNs

In recent years, the increasing variety of nonlinear activation functions (NAFs) in deep neural networks (DNNs) has led to higher computational demands. However, hardware implementation faces challenges such as lack of flexibility, high hardware cost, and limited accuracy. This paper proposes a highly flexible and low-cost hardware solution for implementing activation functions to overcome these issues. Based on the piecewise linear (PWL) approximation method, our method supports NAFs with different accuracy configurations through a customized implementation strategy to meet the requirements in different scenario applications. In this paper, the symmetry of the activation function is investigated, and incorporate curve translation preprocessing and data quantization to significantly reduce hardware storage costs. The modular hardware architecture proposed in this study supports NAFs of multiple accuracies, which is suitable for designing deep learning neural network accelerators in various scenarios, avoiding the need to design dedicated hardware circuits for the activation function layer and enhances circuit design efficiency. The proposed hardware architecture is validated on the Xilinx XC7Z010 development board. The experimental results show that the average absolute error (AAE) is reduced by about 35.6 % at a clock frequency of 312.5 MHz. Additionally, the accuracy loss of the model is maximized to −0.684 % after replacing the activation layer function of DNNs under the PyTorch framework.

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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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