用于量子计算的模 2$^n$ $+$ 1 加法器的新型优化设计

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Bhaskar Gaur;Himanshu Thapliyal
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引用次数: 0

摘要

量子模块加法器是最基本但用途最广的量子计算操作之一。它们有助于实现更高难度的功能,如减法和乘法,这些功能可用于量子密码分析、量子图像处理和安全通信等应用。据我们所知,目前还没有量子模(2^{n}+1$ )加法器(QMA)的设计。在这项工作中,我们提出了四种专门针对模数 ( 2^{n}+1$ ) 加法的量子加法器。这些加法器可以同时提供正则和模数 ( $2^{n}+1$ ) 加法,从而提高了它们在基于残差数系统的算术中的应用。我们的第一个设计 QMA1 是一种新型量子模 ( $2^{n}+1$ ) 加法器。我们提出的第二个加法器 QMA2 优化了 QMA1 中量子门的利用率,使 CNOT 门数减少了 37.5%,CNOT 深度减少了 46.15%,Toffoli 门数和深度均减少了 26.5%。我们提出的第三个加法器 QMA3 使用了零重置,这是一种基于动态电路的量子比特再利用功能,从而节省了 25% 的量子比特数。我们的第四个设计 QMA4 展示了加入额外的零重置以实现更纯净的 $|0$ $\rangle $ 状态,从而减少量子态准备误差的好处。值得注意的是,我们在基于 Eagle R1 架构的 127 量子位量子计算机 IBM Washington 上使用 5 量子位配置的拟议模数 ( $2^{n}+1$ ) 加法器进行了实验,证明 QMA1 的误差减少了 28.8%,具体表现如下:1) 由于 QMA2 中的门/深度减少,误差降低了 18.63%;2) 由于 QMA3 中的量子位减少,误差降低了 2.53%;3) 由于 QMA4 中应用了额外的零重置,误差降低了 7.64%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing
Quantum modular adders are one of the most fundamental yet versatile quantum computation operations. They help implement the functions of higher complexity, such as subtraction and multiplication, which are used in applications, such as quantum cryptanalysis, quantum image processing, and securing communication. To the best of our knowledge, there is no existing design of quantum modulo ( $2^{n}+1$ ) adder (QMA). In this work, we propose four quantum adders targeted specifically for modulo ( $2^{n}+1$ ) addition. These adders can provide both regular and modulo ( $2^{n}+1$ ) sum concurrently, enhancing their application in residue number system-based arithmetic. Our first design, QMA1, is a novel quantum modulo ( $2^{n}+1$ ) adder. The second proposed adder, QMA2, optimizes the utilization of quantum gates within the QMA1, resulting in 37.5% reduced CNOT gate count, 46.15% reduced CNOT depth, and 26.5% decrease in both Toffoli gates and depth. We propose a third adder QMA3 that uses zero resets, a dynamic circuits-based feature that reuses qubits, leading to 25% savings in qubit count. Our fourth design, QMA4, demonstrates the benefit of incorporating additional zero resets to achieve a purer $|0$ $\rangle $ state, reducing quantum state preparation errors. Notably, we conducted experiments using 5-qubit configurations of the proposed modulo ( $2^{n}+1$ ) adders on the IBM Washington, a 127-qubit quantum computer based on the Eagle R1 architecture, to demonstrate a 28.8% reduction in QMA1’s error of which do the following: 1) 18.63% error reduction happens due to gate/depth reduction in QMA2; 2) 2.53% drop in error due to qubit reduction in QMA3; and 3) 7.64% error decreased due to application of additional zero resets in QMA4.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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