基于距离优化 KNN 和 EMD 的脑电图癫痫检测轻量级硬件 IP 核设计

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
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引用次数: 0

摘要

长期有效地检测癫痫发作是癫痫监测和治疗的关键环节。针对可穿戴癫痫检测设备的资源开销问题,本文提出了一种基于可重复使用架构经验模式分解(EMD)和K-近邻(KNN)的癫痫检测轻量级硬件实现方案。首先,利用 EMD 从脑电图(EEG)中提取癫痫特征,并通过可重复使用的架构设计和锯齿变换进行优化,以减少硬件资源的使用。随后,设计了具有相似性判断机制的 KNN 分类器,以提高识别效率。电路采用台积电 65 纳米工艺,面积为 1.91 mm2,工作电压为 1 V,频率为 20 MHz,功耗为 4.034 mW。波恩脑电图数据集的评估结果显示,分类准确率为 96%,灵敏度为 98%,单次检测延迟为 1.51 毫秒。该硬件设计结构简单、准确度高、资源消耗低,适用于可穿戴式癫痫检测设备。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection

Long-term and effective detection of epileptic seizures is a crucial aspect of epilepsy monitoring and treatment. Addressing the resource overhead issue of wearable epilepsy detection devices, this paper proposes a lightweight hardware implementation scheme for epilepsy detection based on a reusable architecture empirical mode decomposition (EMD) and K-Nearest Neighbors (KNN). Firstly, EMD is used to extract epileptic features from electroencephalogram (EEG), optimized through a reusable architecture design and sawtooth transform to reduce hardware resource usage. Subsequently, a KNN classifier with similarity judgment mechanism is designed to improve the recognition efficiency. Implemented on TSMC 65 nm process, the circuit area is 1.91 mm2, operates at 1 V and 20 MHz, with a power consumption of 4.034 mW. Evaluation on the Bonn EEG dataset yielded a classification accuracy of 96 %, sensitivity of 98 %, and a single detection delay of 1.51 ms. The hardware design offers a simple structure, high accuracy, and low resource consumption, making it suitable for wearable epilepsy detection devices.

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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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