Yun Li, Yi Shen, Yue Cao, Mengtong Wu, Li Dang, Shubin Liu, Ruixue Ding, Zhangming Zhu
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Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS
In this paper, an 800 MS/s 12bit voltage-time hybrid domain ADC is presented. A four-channel split time-to-digital converter (TDC) is proposed in the first-stage sub-TDC, effectively reducing the impact of skew error. A configurable time amplifier (TA) is proposed to pre-configure the discharge voltage, optimizing the conversation rate and power consumption. The hybrid domain ADC verified in a 28-nm CMOS process with a core area of 0.033 mm2, which achieves 65.66 dB SNDR and 72.16 dB SFDR while consuming 7.93 mW from a single 0.9-V supply, resulting in Walden figure-of-merit (FoM) values of 6.34 fJ/conversion-step.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
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