为先进的 3D 片上系统制定高效的 ESD 保护策略

Nature Reviews Electrical Engineering Pub Date : 2024-07-16 DOI:10.1038/s44287-024-00071-4

Shih-Hsiang (Shane) Lin, Marko Simicic, Nicolas Pantano

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引用次数: 0

摘要

2.5D/3D 技术要求设计人员减少内部 I/O 接口的静电放电 (ESD) 保护。为避免过度设计 ESD 保护，设计人员需要从根本上了解发生在这一层面的 ESD 事件。在此，我们将为电路设计师和接合工具供应商提供见解、实用指南和研究方向。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

Towards efficient ESD protection strategies for advanced 3D systems-on-chip

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Towards efficient ESD protection strategies for advanced 3D systems-on-chip

2.5D/3D technologies require designers to reduce electrostatic discharge (ESD) protection of the internal I/O interfaces. To avoid over-design of ESD protection, designers require a more fundamental understanding of the ESD events that occur at this level. Here we present insights, practical guidelines and research directions for circuit designers and suppliers of bonding tools.

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Nature Reviews Electrical Engineering

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