Thockchom Birjit Singha;Basa Sanjana;Titu Mary Ignatius;Roy Paily Palathinkal;Shaik Rafi Ahamed
{"title":"利用重新配置的 CFB 模式提高 AES 设计的抗功率攻击能力","authors":"Thockchom Birjit Singha;Basa Sanjana;Titu Mary Ignatius;Roy Paily Palathinkal;Shaik Rafi Ahamed","doi":"10.1109/TVLSI.2024.3422501","DOIUrl":null,"url":null,"abstract":"Advanced encryption standard (AES) is used to secure the communication process on the Internet-of-Things (IoT) hardware. It is implementable in various 128-bit modes, such as electronic code book (ECB), cipher block chaining (CBC), cipher feedback (CFB), output feedback (OFB), and counter (CTR), to facilitate parallel processing of data. The noninvasive nature of power analysis attacks (PAAs) to retrieve secret information off a physical device renders such hardware to be unsafe from the adversaries. Also, the assessment of the aforementioned modes for security remains obscured, which is undertaken by this work as a novel attempt. In addition, this work proposes a novel 64-bit version of CFB mode, which provides the highest security with respect to other modes and several unprotected AES designs. PAAs are performed on ASIC platform utilizing UMC 65-nm technology node and a hardware experimental setup using side-channel attack security evaluation board (SASEBO), both at 16-MHz AES frequency and traces sampled at the rate of 1 GSa/s. The measurements to disclose (MTDs) of >1 000 000 provided by the proposed CFB-64 are significantly more than that provided by usual unprotected AES designs. It also offers the highest MTD, and least signal-to-noise ratio (SNR) and mutual information (MI) among other modes, indicating the highest security. The proposed CFB-64 acts as a countermeasure upon integration with an unprotected AES.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks\",\"authors\":\"Thockchom Birjit Singha;Basa Sanjana;Titu Mary Ignatius;Roy Paily Palathinkal;Shaik Rafi Ahamed\",\"doi\":\"10.1109/TVLSI.2024.3422501\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advanced encryption standard (AES) is used to secure the communication process on the Internet-of-Things (IoT) hardware. It is implementable in various 128-bit modes, such as electronic code book (ECB), cipher block chaining (CBC), cipher feedback (CFB), output feedback (OFB), and counter (CTR), to facilitate parallel processing of data. The noninvasive nature of power analysis attacks (PAAs) to retrieve secret information off a physical device renders such hardware to be unsafe from the adversaries. Also, the assessment of the aforementioned modes for security remains obscured, which is undertaken by this work as a novel attempt. In addition, this work proposes a novel 64-bit version of CFB mode, which provides the highest security with respect to other modes and several unprotected AES designs. PAAs are performed on ASIC platform utilizing UMC 65-nm technology node and a hardware experimental setup using side-channel attack security evaluation board (SASEBO), both at 16-MHz AES frequency and traces sampled at the rate of 1 GSa/s. The measurements to disclose (MTDs) of >1 000 000 provided by the proposed CFB-64 are significantly more than that provided by usual unprotected AES designs. It also offers the highest MTD, and least signal-to-noise ratio (SNR) and mutual information (MI) among other modes, indicating the highest security. The proposed CFB-64 acts as a countermeasure upon integration with an unprotected AES.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10596060/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10596060/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks
Advanced encryption standard (AES) is used to secure the communication process on the Internet-of-Things (IoT) hardware. It is implementable in various 128-bit modes, such as electronic code book (ECB), cipher block chaining (CBC), cipher feedback (CFB), output feedback (OFB), and counter (CTR), to facilitate parallel processing of data. The noninvasive nature of power analysis attacks (PAAs) to retrieve secret information off a physical device renders such hardware to be unsafe from the adversaries. Also, the assessment of the aforementioned modes for security remains obscured, which is undertaken by this work as a novel attempt. In addition, this work proposes a novel 64-bit version of CFB mode, which provides the highest security with respect to other modes and several unprotected AES designs. PAAs are performed on ASIC platform utilizing UMC 65-nm technology node and a hardware experimental setup using side-channel attack security evaluation board (SASEBO), both at 16-MHz AES frequency and traces sampled at the rate of 1 GSa/s. The measurements to disclose (MTDs) of >1 000 000 provided by the proposed CFB-64 are significantly more than that provided by usual unprotected AES designs. It also offers the highest MTD, and least signal-to-noise ratio (SNR) and mutual information (MI) among other modes, indicating the highest security. The proposed CFB-64 acts as a countermeasure upon integration with an unprotected AES.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.