使用有源电感器的宽调谐范围 CMOS 差分环形 VCO,适用于无线应用

IF 1.8 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Mahdi Alijani, Mohammadmahdi Javanmardi, Adib Abrishamifar
{"title":"使用有源电感器的宽调谐范围 CMOS 差分环形 VCO,适用于无线应用","authors":"Mahdi Alijani, Mohammadmahdi Javanmardi, Adib Abrishamifar","doi":"10.1002/cta.4155","DOIUrl":null,"url":null,"abstract":"A differential ring voltage‐controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low‐noise and high‐quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180‐nm CMOS technology with a 1.8‐V voltage source (<jats:italic>V</jats:italic><jats:sub>DD</jats:sub>). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm<jats:sup>2</jats:sup>. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":1.8000,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications\",\"authors\":\"Mahdi Alijani, Mohammadmahdi Javanmardi, Adib Abrishamifar\",\"doi\":\"10.1002/cta.4155\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A differential ring voltage‐controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low‐noise and high‐quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180‐nm CMOS technology with a 1.8‐V voltage source (<jats:italic>V</jats:italic><jats:sub>DD</jats:sub>). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm<jats:sup>2</jats:sup>. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.\",\"PeriodicalId\":13874,\"journal\":{\"name\":\"International Journal of Circuit Theory and Applications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.8000,\"publicationDate\":\"2024-07-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Circuit Theory and Applications\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1002/cta.4155\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Circuit Theory and Applications","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1002/cta.4155","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本文提出的差分环压控振荡器(DRVCO)是通信系统的关键模块之一。它由四级延迟单元链式连接而成,形成一个带有辅助路径互连的环形结构。DRVCO 的振荡频率可通过调节控制充电电流的调谐电压来控制。为了实现无线应用所需的性能,首次在每个延迟单元中采用了低噪声、高品质系数的吴有源电感器。使用有源电感器可提供宽调谐范围,还能实现适当的相位噪声和低功耗。所提出的电路采用 1.8 V 电压源 (VDD) 的标准 180-nm CMOS 技术进行设计和仿真。电路设计的调谐范围为 2.15 GHz,中心频率振荡为 2.745 GHz,控制电压变化范围为 1.4 V(0 至 1.4 V)。为达到预期性能,电路的平均功耗为 1.99 mW。在 1 MHz 偏移频率下,它的相位噪声为 - 91.2 dBc/Hz,表明噪声得到了有效抑制。电路的优点系数(FoM)为 - 156.9 dBc/Hz,代表了电路的整体性能。电路的最终布局估计面积为 0.00072 平方毫米。为确保拟议电路的可靠性能,我们进行了各种分析,包括蒙特卡洛模拟、PVT(工艺、电压、温度)变化分析和其他相关分析。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications
A differential ring voltage‐controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low‐noise and high‐quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180‐nm CMOS technology with a 1.8‐V voltage source (VDD). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm2. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.
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来源期刊
International Journal of Circuit Theory and Applications
International Journal of Circuit Theory and Applications 工程技术-工程:电子与电气
CiteScore
3.60
自引率
34.80%
发文量
277
审稿时长
4.5 months
期刊介绍: The scope of the Journal comprises all aspects of the theory and design of analog and digital circuits together with the application of the ideas and techniques of circuit theory in other fields of science and engineering. Examples of the areas covered include: Fundamental Circuit Theory together with its mathematical and computational aspects; Circuit modeling of devices; Synthesis and design of filters and active circuits; Neural networks; Nonlinear and chaotic circuits; Signal processing and VLSI; Distributed, switched and digital circuits; Power electronics; Solid state devices. Contributions to CAD and simulation are welcome.
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