减少加密开销的安全边缘编码信令物联网收发器

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mizan Abraha Gebremicheal;Ibrahim M. Elfadel
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引用次数: 0

摘要

边缘编码信令(ECS)协议利用两个重要的神经形态属性在物联网设备和传感器中实现单线信令。首先是将比特编码为脉冲(尖峰)流,其次是在接收器上规避时钟和数据恢复(CDR)。此外,ECS 还可以使用超低延迟版本的 A5/1 流密码,具有强大而轻巧的安全功能。这种强大的安全性是以降低数据传输速率和显著的面积开销为代价的。在本文中,我们介绍了新一代安全 ECS 协议,其中包含两项显著改进。首先是更紧凑的脉冲流定义,从而提高了普通 ECS 协议的数据传输率。其次是低延迟 A5/1 流密码的编码感知版本,它对传输的有效数据速率影响最小。因此,我们提出了一种全新的全数字安全 ECS 收发器设计,并在 65 纳米技术中进行了原型设计和功能验证。与前几代安全 ECS 收发器相比,这种新设计的最低、平均和最高数据传输速率分别提高了约 138%、199% 和 640%,对暴力破解攻击的抵御能力提高了 16 倍。此外,ASIC 实现表明,它保持了 ECS 架构的紧凑和高能效特性,仅使用 28~\mu $ W,平均能效为 2.745 pJ/bit,门数约为 2880 门。与上一代安全 ECS 相比,等效门数减少了 40% 以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead
The edge-coded signaling (ECS) protocol enables single-wire signaling in IoT devices and sensors using two important neuromorphic attributes. The first is the coding of bits as a stream of pulses (spikes), and the second is the circumvention of clock and data recovery (CDR) at the receiver. In addition, ECS can be endowed with strong, yet lightweight, security features using an ultralow-latency version of the A5/1 stream cipher. Such strong security comes at the expense of decreased data rates and significant area overhead. In this article, we introduce a new generation of secure ECS protocols that incorporates two notable improvements. The first is a more compact pulse stream definition that results in improved data rates for the plain ECS protocol. The second is a coding-aware version of the low-latency A5/1 stream cipher that results in minimal impact on the effective data rate of the transmission. Consequently, a new all-digital and secure ECS transceiver design is proposed, prototyped, and functionally verified in 65-nm technology. Compared with previous generations of secure ECS transceivers, this new design achieves an increase of approximately 138%, 199%, and 640% in minimum, average, and maximum data rates, respectively, and results in increased resiliency against brute-force attacks by a factor of 16. Furthermore, the ASIC implementation shows that it maintains the compact and energy-efficient features of the ECS architecture, using only $28~\mu $ W with an average energy efficiency of 2.745 pJ/bit and a gate count of approximately 2880 gates. This is more than 40% decrease in the equivalent gate count relative to the previous secure ECS generation.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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