Ultra8T: A sub-threshold 8T SRAM with leakage detection

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing the sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage ($V_{DDMIN}$). In this work, we first propose a model that describes a specific relationship between read current and leakage noise in a given column. Based on the model, Ultra8T SRAM is designed to aggressively reduce $V_{DDMIN}$ by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256 × 64 array in 28 nm CMOS technology. Post-simulation results show successful read operation at 0.25 V with 1.11 $\mu$s read delay, and the minimum energy required is 1.69 pJ at 0.4 V