具有低损耗 CM 返回路径的 28 纳米双模显式 F$_{23}$ 类 VCO,可在 4.9-7.3-GHz TR 范围内实现 70-400-kHz 1/$f^{3}$ PN 波角

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Shan Lu;Danyu Wu;Xuan Guo;Hanbo Jia;Yong Chen;Xinyu Liu
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引用次数: 0

摘要

本简介介绍了一种明确的 F23 类压控振荡器(VCO)。通过波形整形获得方形电压波形,并通过适当的共模(CM)返回路径抑制闪烁噪声上变频。二次谐波频率处的 CM 谐振由一个紧凑的八角形电感器引入。通过 F23 类工作,脉冲灵敏度函数 (ISF) 的均方根值显著降低。VCO 可在高阶 LC 谐振器的两种模式之间切换,高阶 LC 谐振器由两个通过电容器耦合的相同 LC 槽组成。VCO 原型采用 28 纳米 CMOS 实现。测量结果表明,其连续调谐范围 (TR) 为 4.89-7.29 GHz,在 5.8 GHz 时的峰值优越性 (FoM) 为 190.5 dB/Hz,在整个 TR 范围内优于 188.5 dB。闪烁相噪角范围为 70 至 400 kHz。VCO 在 0.5 V 电源下的功耗为 16-19 mW,占用的有效面积为 0.21 mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70–400-kHz 1/f³ PN Corner Over 4.9–7.3-GHz TR
This brief presents an explicit Class-F23 voltage-controlled oscillator (VCO). The square-like voltage waveform is obtained via waveform shaping, and flicker noise upconversion is suppressed by a proper common-mode (CM) return path. CM resonance at the second harmonic frequency is introduced by a compact octagonal inductor. The rms value of the impulse sensitivity function (ISF) is significantly reduced through Class-F23 operation. The VCO switches between two modes of a high-order LC resonator consisting of two identical LC tanks coupled by capacitors. A prototype of the VCO is implemented in a 28-nm CMOS. Measurements show a continuous tuning range (TR) of 4.89–7.29 GHz, with a peak figure of merit (FoM) of 190.5 dB/Hz at 5.8 GHz and better than 188.5 dB across the entire TR. The flicker phase-noise corner ranges from 70 to 400 kHz. The VCO consumes 16–19 mW from a 0.5-V supply and occupies an active area of 0.21 mm2.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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