{"title":"带有两级 SC DAC 的注入锁定和子采样时钟乘法器,抖动变化率为 2.67","authors":"Qifeng Huang;Siji Huang;Yanhang Chen;Yifei Fan;Jie Yuan","doi":"10.1109/TVLSI.2024.3417015","DOIUrl":null,"url":null,"abstract":"This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to-analog converter (DAC). Conventionally, the DAC resolution needs to be increased for low noise at the cost of degraded monotonicity due to device mismatch. To overcome this tradeoff, the proposed DAC utilizes the SC technique to achieve fine steps. With only two capacitors involved in charge transfer, the DAC is inherently monotonic, avoiding the boundary-crossing issue and the mismatch calibration. A control-voltage-tracking loop (CVTL) further suppresses the quantization noise by balancing the up and down step sizes and helps achieve a 16-bit-level voltage step. The FTL is sub-sampling and utilizes a bang-bang phase detector (BBPD). Locking at 700 MHz, the ILCM achieves a 0.9-ps integrated jitter, a -125-dBc/Hz phase noise at a 1-MHz offset, and a small jitter variation of 2.67% under different supply voltages and temperatures. With FTL, the spur is around -56 dBc from the prototype fabricated in a 180-nm CMOS process. The chip occupies a core area of 0.054 mm2 and consumes \n<inline-formula> <tex-math>$689~\\mu $ </tex-math></inline-formula>\nW from a 1.8-V supply, achieving an FoM of -242.5 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation\",\"authors\":\"Qifeng Huang;Siji Huang;Yanhang Chen;Yifei Fan;Jie Yuan\",\"doi\":\"10.1109/TVLSI.2024.3417015\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to-analog converter (DAC). Conventionally, the DAC resolution needs to be increased for low noise at the cost of degraded monotonicity due to device mismatch. To overcome this tradeoff, the proposed DAC utilizes the SC technique to achieve fine steps. With only two capacitors involved in charge transfer, the DAC is inherently monotonic, avoiding the boundary-crossing issue and the mismatch calibration. A control-voltage-tracking loop (CVTL) further suppresses the quantization noise by balancing the up and down step sizes and helps achieve a 16-bit-level voltage step. The FTL is sub-sampling and utilizes a bang-bang phase detector (BBPD). Locking at 700 MHz, the ILCM achieves a 0.9-ps integrated jitter, a -125-dBc/Hz phase noise at a 1-MHz offset, and a small jitter variation of 2.67% under different supply voltages and temperatures. With FTL, the spur is around -56 dBc from the prototype fabricated in a 180-nm CMOS process. The chip occupies a core area of 0.054 mm2 and consumes \\n<inline-formula> <tex-math>$689~\\\\mu $ </tex-math></inline-formula>\\nW from a 1.8-V supply, achieving an FoM of -242.5 dB.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10571831/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10571831/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation
This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to-analog converter (DAC). Conventionally, the DAC resolution needs to be increased for low noise at the cost of degraded monotonicity due to device mismatch. To overcome this tradeoff, the proposed DAC utilizes the SC technique to achieve fine steps. With only two capacitors involved in charge transfer, the DAC is inherently monotonic, avoiding the boundary-crossing issue and the mismatch calibration. A control-voltage-tracking loop (CVTL) further suppresses the quantization noise by balancing the up and down step sizes and helps achieve a 16-bit-level voltage step. The FTL is sub-sampling and utilizes a bang-bang phase detector (BBPD). Locking at 700 MHz, the ILCM achieves a 0.9-ps integrated jitter, a -125-dBc/Hz phase noise at a 1-MHz offset, and a small jitter variation of 2.67% under different supply voltages and temperatures. With FTL, the spur is around -56 dBc from the prototype fabricated in a 180-nm CMOS process. The chip occupies a core area of 0.054 mm2 and consumes
$689~\mu $
W from a 1.8-V supply, achieving an FoM of -242.5 dB.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.