SiO2‐GaN Interface Improvement by Wet Cleaning and In Situ Annealing for GaN MOS Transistors

Herein, ex situ wet cleaning and in situ high‐temperature annealing of GaN surfaces prior to low pressure chemical vapor deposition (LPCVD) of the SiO2 gate oxide, aiming at effective SiO2‐GaN interface engineering for channel improvement of metal–oxide semiconductor (MOS) transistors, are investigated. Additionally, the combination of in situ annealing and gate oxide deposition in an LPCVD tool provides the advantage of an industrially preferred batch process. A strong impact of the pretreatments on the interface state density and flatband voltage of the fabricated n‐type GaN MOS capacitors is demonstrated. Combined HF wet cleaning and NH annealing result in a low peak interface state density and a close to ideal C–V curve with a nearly ideal flatband voltage . Furthermore, the I–V characteristics exhibit a positive voltage shift of the current onset and substantially reduced I‐V hysteresis, i.e., negligible temporary charging. Physical root causes are assumed to be reduced contamination due to nondestructive yet efficient HF cleaning combined with subsequent high temperatures and the reduction of near‐interface, quasi‐permanent traps due to the saturation of dangling bonds by the annealing in hydrogen‐containing atmosphere.