基于深度强化学习的芯片组多核系统电源管理

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Xiao Li;Lin Chen;Shixi Chen;Fan Jiang;Chengeng Li;Wei Zhang;Jiang Xu
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引用次数: 0

摘要

随着摩尔定律的放缓,芯片组技术已成为满足日益增长的高性能计算需求的一种有前途的解决方案。基于芯片组的多核系统通过异构集成提供了更高的性能,但同时也给功率传输系统(PDS)的设计带来了挑战。额外的垂直和芯片间连接的集成以及更高的功率密度,对功率传输提出了严格的要求。此外,PDS 效率还会受到运行时工作负载变化的影响,因此有必要将 PDS 和处理器作为一个整体进行设计和管理,以提高系统能效,同时兼顾性能。本文提出了一种离线-在线协同设计优化方法,将离线 PDS 设计优化与在线功耗管理相结合。为解决功耗和交付不匹配问题,我们引入了一种基于深度 Q 网络(DQN)的集中式在线控制方案,用于基于芯片组的多核系统中的功耗协同管理。通过精心设计状态空间和奖励函数,我们的方法实现了工作负载感知自适应控制,从而在给定性能目标(PT)下保持 PDS 效率的同时降低能耗延迟积(EDP)。我们在实际应用中进行了评估,以验证我们方法的有效性。对于 64 核系统,我们的方法在满足 90% 的性能目标的同时,实现了 67% 的平均 EDP 降低率,比基于模块化 Q 学习(MQL)和启发式的先进方法分别高出 4% 和 16%。此外,与基于 MQL 的方法相比,我们的方法展示了更明智的行动选择策略、更高的控制稳定性和更低的实施开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems
Chiplet technology has emerged as a promising solution to address the increasing demand for high-performance computing in light of the slowdown of Moore’s law. While chiplet-based multicore systems offer higher performance through heterogeneous integration, they also pose challenges for power delivery system (PDS) design. The integration of additional vertical and inter-chiplet connections, along with higher power density, impose stringent requirements on power delivery. Moreover, PDS efficiency is affected by workload variations at runtime, necessitating the need to design and manage PDSs and processors as a whole to improve system energy efficiency while balancing performance. In this article, we propose an offline-online co-design optimization methodology that combines offline PDS design optimization with online power management. To address the power consumption and delivery mismatch, we introduce a centralized deep Q-network (DQN)-based online control scheme for power co-management in chiplet-based multicore systems. By carefully designing the state space and reward functions, our approach achieves workload-aware adaptive control to reduce the energy-delay-product (EDP) while maintaining PDS efficiency under a given performance target (PT). We conduct evaluations on realistic applications to validate the effectiveness of our approach. For 64-core systems, our method achieves an average EDP reduction of 67% while meeting a 90% PT, surpassing state-of-the-art modular Q-learning (MQL)-based and heuristic-based approaches by up to 4% and 16%, respectively. Additionally, our approach demonstrates wiser action selection policies, higher control stability, and lower implementation overhead compared to the MQL-based approach.
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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