{"title":"用于数据转换器电路的高速、高能效 CMOS 动态比较器","authors":"K. Brindha, J. Manjula","doi":"10.1002/jnm.3263","DOIUrl":null,"url":null,"abstract":"<p>Complementary metal oxide semiconductor (CMOS) comparators play a pivotal role in analog and mixed-signal circuits, finding diverse applications across electronic systems. In data converter circuits, the significance of high-speed, low-power comparators is pronounced. They ensure swift and precise signal comparisons, minimizing energy usage for dependable analog-to-digital and digital-to-analog conversions. This paper introduces an advanced CMOS dynamic comparator, optimized for data converter circuits using a 45 nm CMOS process. The comparator integrates two novel designs tailored for operation at 0.8 and 1 V power supplies, functioning at 1 GHz. One design incorporates a cascode differential amplifier in the pre-amplifier stage, enhancing speed and sensitivity by augmenting gain, linearity, and output swing. This approach achieves a delay of 73.53 ps and consumes 9.95 μW at a 1 V supply voltage. The second design employs a simple charge pump in the pre-amplifier stage, further elevating speed and sensitivity through amplified voltage levels and enhanced slew rate, resulting in a 57.24 ps delay and 9.03 μW power consumption at 1 V. Simulations underscore the proposed comparator's superiority over conventional counterparts, showcasing significant enhancements in speed and power efficiency, all while preserving precision and dependability.</p>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 4","pages":""},"PeriodicalIF":1.6000,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A high-speed and power efficient CMOS dynamic comparator for data converter circuits\",\"authors\":\"K. Brindha, J. Manjula\",\"doi\":\"10.1002/jnm.3263\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>Complementary metal oxide semiconductor (CMOS) comparators play a pivotal role in analog and mixed-signal circuits, finding diverse applications across electronic systems. In data converter circuits, the significance of high-speed, low-power comparators is pronounced. They ensure swift and precise signal comparisons, minimizing energy usage for dependable analog-to-digital and digital-to-analog conversions. This paper introduces an advanced CMOS dynamic comparator, optimized for data converter circuits using a 45 nm CMOS process. The comparator integrates two novel designs tailored for operation at 0.8 and 1 V power supplies, functioning at 1 GHz. One design incorporates a cascode differential amplifier in the pre-amplifier stage, enhancing speed and sensitivity by augmenting gain, linearity, and output swing. This approach achieves a delay of 73.53 ps and consumes 9.95 μW at a 1 V supply voltage. The second design employs a simple charge pump in the pre-amplifier stage, further elevating speed and sensitivity through amplified voltage levels and enhanced slew rate, resulting in a 57.24 ps delay and 9.03 μW power consumption at 1 V. Simulations underscore the proposed comparator's superiority over conventional counterparts, showcasing significant enhancements in speed and power efficiency, all while preserving precision and dependability.</p>\",\"PeriodicalId\":50300,\"journal\":{\"name\":\"International Journal of Numerical Modelling-Electronic Networks Devices and Fields\",\"volume\":\"37 4\",\"pages\":\"\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2024-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Numerical Modelling-Electronic Networks Devices and Fields\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1002/jnm.3263\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1002/jnm.3263","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
摘要
互补金属氧化物半导体(CMOS)比较器在模拟和混合信号电路中发挥着举足轻重的作用,在电子系统中有着多种多样的应用。在数据转换器电路中,高速、低功耗比较器的重要性不言而喻。它们能确保快速、精确的信号比较,最大限度地降低能耗,从而实现可靠的模数和数模转换。本文介绍了一种先进的 CMOS 动态比较器,它针对使用 45 纳米 CMOS 工艺的数据转换器电路进行了优化。该比较器集成了两个新颖的设计,适合在 0.8 V 和 1 V 电源下运行,工作频率为 1 GHz。其中一种设计在前置放大器级中集成了级联差分放大器,通过增强增益、线性度和输出摆幅来提高速度和灵敏度。这种方法的延迟时间为 73.53 ps,在 1 V 电源电压下的功耗为 9.95 μW。第二种设计在前置放大器级采用了一个简单的电荷泵,通过放大电压电平和增强的压摆率进一步提高了速度和灵敏度,从而在 1 V 电压下实现了 57.24 ps 的延迟和 9.03 μW 的功耗。仿真结果表明,拟议的比较器优于传统的比较器,在保持精度和可靠性的同时,显著提高了速度和能效。
A high-speed and power efficient CMOS dynamic comparator for data converter circuits
Complementary metal oxide semiconductor (CMOS) comparators play a pivotal role in analog and mixed-signal circuits, finding diverse applications across electronic systems. In data converter circuits, the significance of high-speed, low-power comparators is pronounced. They ensure swift and precise signal comparisons, minimizing energy usage for dependable analog-to-digital and digital-to-analog conversions. This paper introduces an advanced CMOS dynamic comparator, optimized for data converter circuits using a 45 nm CMOS process. The comparator integrates two novel designs tailored for operation at 0.8 and 1 V power supplies, functioning at 1 GHz. One design incorporates a cascode differential amplifier in the pre-amplifier stage, enhancing speed and sensitivity by augmenting gain, linearity, and output swing. This approach achieves a delay of 73.53 ps and consumes 9.95 μW at a 1 V supply voltage. The second design employs a simple charge pump in the pre-amplifier stage, further elevating speed and sensitivity through amplified voltage levels and enhanced slew rate, resulting in a 57.24 ps delay and 9.03 μW power consumption at 1 V. Simulations underscore the proposed comparator's superiority over conventional counterparts, showcasing significant enhancements in speed and power efficiency, all while preserving precision and dependability.
期刊介绍:
Prediction through modelling forms the basis of engineering design. The computational power at the fingertips of the professional engineer is increasing enormously and techniques for computer simulation are changing rapidly. Engineers need models which relate to their design area and which are adaptable to new design concepts. They also need efficient and friendly ways of presenting, viewing and transmitting the data associated with their models.
The International Journal of Numerical Modelling: Electronic Networks, Devices and Fields provides a communication vehicle for numerical modelling methods and data preparation methods associated with electrical and electronic circuits and fields. It concentrates on numerical modelling rather than abstract numerical mathematics.
Contributions on numerical modelling will cover the entire subject of electrical and electronic engineering. They will range from electrical distribution networks to integrated circuits on VLSI design, and from static electric and magnetic fields through microwaves to optical design. They will also include the use of electrical networks as a modelling medium.