{"title":"设计用于 2.6 μm 波长 SWIR 图像传感器应用的 128 × 128 ROIC 阵列原型","authors":"Hyeon-June Kim","doi":"10.1016/j.vlsi.2024.102232","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents the development and evaluation of a 128 × 128 Readout Integrated Circuit (ROIC) prototype, engineered for Short-Wave Infrared (SWIR) imaging at a specific target wavelength of 2.6 μm. Employing silicon-level verification, this work undertook an exhaustive analysis of the ROIC's performance, identifying key areas for enhancement to improve SWIR imaging systems. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) Focal Plane Arrays (FPAs), facilitating high-resolution imaging. The prototype consumes 42.25 mW of power and achieves a frame rate of 390 frames per second. The fabricated chip show that the random noise level is 72.65 μVrms and Pixel-FPN is 21 LSBrms. This investigation lays a critical groundwork for future SWIR imaging advancements, providing valuable insights and methodologies to boost imaging performance in various applications.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2024-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications\",\"authors\":\"Hyeon-June Kim\",\"doi\":\"10.1016/j.vlsi.2024.102232\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper presents the development and evaluation of a 128 × 128 Readout Integrated Circuit (ROIC) prototype, engineered for Short-Wave Infrared (SWIR) imaging at a specific target wavelength of 2.6 μm. Employing silicon-level verification, this work undertook an exhaustive analysis of the ROIC's performance, identifying key areas for enhancement to improve SWIR imaging systems. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) Focal Plane Arrays (FPAs), facilitating high-resolution imaging. The prototype consumes 42.25 mW of power and achieves a frame rate of 390 frames per second. The fabricated chip show that the random noise level is 72.65 μVrms and Pixel-FPN is 21 LSBrms. This investigation lays a critical groundwork for future SWIR imaging advancements, providing valuable insights and methodologies to boost imaging performance in various applications.</p></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2024-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926024000968\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926024000968","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications
This paper presents the development and evaluation of a 128 × 128 Readout Integrated Circuit (ROIC) prototype, engineered for Short-Wave Infrared (SWIR) imaging at a specific target wavelength of 2.6 μm. Employing silicon-level verification, this work undertook an exhaustive analysis of the ROIC's performance, identifying key areas for enhancement to improve SWIR imaging systems. Fabricated with 0.18-μm CMOS technology, the ROIC is tailored for integration with Indium Gallium Arsenide (InGaAs) Focal Plane Arrays (FPAs), facilitating high-resolution imaging. The prototype consumes 42.25 mW of power and achieves a frame rate of 390 frames per second. The fabricated chip show that the random noise level is 72.65 μVrms and Pixel-FPN is 21 LSBrms. This investigation lays a critical groundwork for future SWIR imaging advancements, providing valuable insights and methodologies to boost imaging performance in various applications.
期刊介绍：
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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