{"title":"基于二氧化钛/硅的先进太阳能电池结构分析:提高光伏参数和热稳定性","authors":"Dibyendu Kumar Ghosh, Shiladitya Acharyya, Sukanta Bose, Gourab Das, Sumita Mukhopadhyay, Anindita Sengupta","doi":"10.1007/s12633-024-03063-z","DOIUrl":null,"url":null,"abstract":"<div><p>In this contribution, Automat FOR Simulation of HETero-structures v2.5 software was used for unveiling the photovoltaic performance and thermal stability of relatively less explored TiO<sub>2</sub>/c-Si heterojunction solar cell architecture based on 110 μm wafers. Firstly, the dependence of the photovoltaic performance on the emitter layer, i.e. the TiO<sub>2</sub> layer, was explored by varying its different characteristics: thickness, carrier concentration and the defect density at the TiO<sub>2</sub>/Si interface. The study revealed that the power conversion efficiency might be as high as 16.34% (even without any interfacial passivation layer) even when the thickness of the wafer was kept at 110 μm; the thickness and the doping concentration of the TiO<sub>2</sub> emitter layer were kept as 7 nm and 1 × 10<sup>20</sup> cm<sup>−3</sup>; respectively. The corresponding defect density at the TiO<sub>2</sub>/p-Si interface was 1 × 10<sup>12</sup> cm<sup>−2</sup>. Furthermore, a significant gain in the power output was realized by embedding either poly-silicon on oxide or carrier selective contact layer at the rear side of the device architecture. In the case of the incorporation of poly-silicon on the oxide structure at the rear side of the metal/c-Si interface, the role of the ultra-thin tunnel oxide thickness on the device's performance was explored in detail. Next, the poly-silicon on oxide structure was replaced by the NiO<sub>x</sub> layer, an efficient hole transport layer at the rear side of the device architecture. Various performance-affecting parameters, such as NiO<sub>x</sub> thickness, NiO<sub>x</sub> band gap, and the defect density at the NiO<sub>x</sub>/Si interface, were varied at different carrier concentrations of the NiO<sub>x</sub> layer to obtain the best possible conditions for realizing the maximum power output. The study was further extended to examine the influence of the wafer lifetime on the device performance of all the simulated solar cells. Eventually, the device temperature was varied from 275 to 375 K with an interval of 25 K to investigate the thermal stability of the proposed cell architectures so that the best possible architecture could be selected for practical fabrication both in terms of photovoltaic performance and thermal stability.</p></div>","PeriodicalId":2,"journal":{"name":"ACS Applied Bio Materials","volume":null,"pages":null},"PeriodicalIF":4.6000,"publicationDate":"2024-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analysis of Advanced TiO2/Si based Solar Cell Architecture: Improving PV Parameters and Thermal Stability\",\"authors\":\"Dibyendu Kumar Ghosh, Shiladitya Acharyya, Sukanta Bose, Gourab Das, Sumita Mukhopadhyay, Anindita Sengupta\",\"doi\":\"10.1007/s12633-024-03063-z\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>In this contribution, Automat FOR Simulation of HETero-structures v2.5 software was used for unveiling the photovoltaic performance and thermal stability of relatively less explored TiO<sub>2</sub>/c-Si heterojunction solar cell architecture based on 110 μm wafers. Firstly, the dependence of the photovoltaic performance on the emitter layer, i.e. the TiO<sub>2</sub> layer, was explored by varying its different characteristics: thickness, carrier concentration and the defect density at the TiO<sub>2</sub>/Si interface. The study revealed that the power conversion efficiency might be as high as 16.34% (even without any interfacial passivation layer) even when the thickness of the wafer was kept at 110 μm; the thickness and the doping concentration of the TiO<sub>2</sub> emitter layer were kept as 7 nm and 1 × 10<sup>20</sup> cm<sup>−3</sup>; respectively. The corresponding defect density at the TiO<sub>2</sub>/p-Si interface was 1 × 10<sup>12</sup> cm<sup>−2</sup>. Furthermore, a significant gain in the power output was realized by embedding either poly-silicon on oxide or carrier selective contact layer at the rear side of the device architecture. In the case of the incorporation of poly-silicon on the oxide structure at the rear side of the metal/c-Si interface, the role of the ultra-thin tunnel oxide thickness on the device's performance was explored in detail. Next, the poly-silicon on oxide structure was replaced by the NiO<sub>x</sub> layer, an efficient hole transport layer at the rear side of the device architecture. Various performance-affecting parameters, such as NiO<sub>x</sub> thickness, NiO<sub>x</sub> band gap, and the defect density at the NiO<sub>x</sub>/Si interface, were varied at different carrier concentrations of the NiO<sub>x</sub> layer to obtain the best possible conditions for realizing the maximum power output. The study was further extended to examine the influence of the wafer lifetime on the device performance of all the simulated solar cells. Eventually, the device temperature was varied from 275 to 375 K with an interval of 25 K to investigate the thermal stability of the proposed cell architectures so that the best possible architecture could be selected for practical fabrication both in terms of photovoltaic performance and thermal stability.</p></div>\",\"PeriodicalId\":2,\"journal\":{\"name\":\"ACS Applied Bio Materials\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":4.6000,\"publicationDate\":\"2024-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ACS Applied Bio Materials\",\"FirstCategoryId\":\"88\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s12633-024-03063-z\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"MATERIALS SCIENCE, BIOMATERIALS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACS Applied Bio Materials","FirstCategoryId":"88","ListUrlMain":"https://link.springer.com/article/10.1007/s12633-024-03063-z","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"MATERIALS SCIENCE, BIOMATERIALS","Score":null,"Total":0}
Analysis of Advanced TiO2/Si based Solar Cell Architecture: Improving PV Parameters and Thermal Stability
In this contribution, Automat FOR Simulation of HETero-structures v2.5 software was used for unveiling the photovoltaic performance and thermal stability of relatively less explored TiO2/c-Si heterojunction solar cell architecture based on 110 μm wafers. Firstly, the dependence of the photovoltaic performance on the emitter layer, i.e. the TiO2 layer, was explored by varying its different characteristics: thickness, carrier concentration and the defect density at the TiO2/Si interface. The study revealed that the power conversion efficiency might be as high as 16.34% (even without any interfacial passivation layer) even when the thickness of the wafer was kept at 110 μm; the thickness and the doping concentration of the TiO2 emitter layer were kept as 7 nm and 1 × 1020 cm−3; respectively. The corresponding defect density at the TiO2/p-Si interface was 1 × 1012 cm−2. Furthermore, a significant gain in the power output was realized by embedding either poly-silicon on oxide or carrier selective contact layer at the rear side of the device architecture. In the case of the incorporation of poly-silicon on the oxide structure at the rear side of the metal/c-Si interface, the role of the ultra-thin tunnel oxide thickness on the device's performance was explored in detail. Next, the poly-silicon on oxide structure was replaced by the NiOx layer, an efficient hole transport layer at the rear side of the device architecture. Various performance-affecting parameters, such as NiOx thickness, NiOx band gap, and the defect density at the NiOx/Si interface, were varied at different carrier concentrations of the NiOx layer to obtain the best possible conditions for realizing the maximum power output. The study was further extended to examine the influence of the wafer lifetime on the device performance of all the simulated solar cells. Eventually, the device temperature was varied from 275 to 375 K with an interval of 25 K to investigate the thermal stability of the proposed cell architectures so that the best possible architecture could be selected for practical fabrication both in terms of photovoltaic performance and thermal stability.