{"title":"利用三元件嵌入式内核的 194-GHz 三级差分驱动器放大器,采用 65-Nm CMOS,频率接近最大值","authors":"Fei He;Qian Xie;Zheng Wang","doi":"10.1109/LMWT.2024.3384700","DOIUrl":null,"url":null,"abstract":"In this letter, we introduce a 194-GHz three-stage differential driver amplifier operating at near-\n<inline-formula> <tex-math>$f_{\\mathrm {max}}$ </tex-math></inline-formula>\n frequencies. To address practical considerations associated with implementing ON-chip embedding elements within the sub-THz frequency range, we employ a three-element embedded core consisting of three types of embedding networks. This design approach offers greater flexibility in selecting the required embedding elements. Based on the proposed embedded core, a three-stage drive amplifier is implemented in the 65-nm CMOS process. The measurement results indicate that the proposed amplifier exhibits a small signal gain of 20.4 dB, a \n<inline-formula> <tex-math>$P_{\\mathrm {sat}}$ </tex-math></inline-formula>\n of −2.1 dBm, and a peak PAE of 2.2% at 194 GHz.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 194-GHz Three-Stage Differential Driver Amplifier Utilizing a Three-Element Embedded Core at Near-fmax Frequencies in 65-Nm CMOS\",\"authors\":\"Fei He;Qian Xie;Zheng Wang\",\"doi\":\"10.1109/LMWT.2024.3384700\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this letter, we introduce a 194-GHz three-stage differential driver amplifier operating at near-\\n<inline-formula> <tex-math>$f_{\\\\mathrm {max}}$ </tex-math></inline-formula>\\n frequencies. To address practical considerations associated with implementing ON-chip embedding elements within the sub-THz frequency range, we employ a three-element embedded core consisting of three types of embedding networks. This design approach offers greater flexibility in selecting the required embedding elements. Based on the proposed embedded core, a three-stage drive amplifier is implemented in the 65-nm CMOS process. The measurement results indicate that the proposed amplifier exhibits a small signal gain of 20.4 dB, a \\n<inline-formula> <tex-math>$P_{\\\\mathrm {sat}}$ </tex-math></inline-formula>\\n of −2.1 dBm, and a peak PAE of 2.2% at 194 GHz.\",\"PeriodicalId\":73297,\"journal\":{\"name\":\"IEEE microwave and wireless technology letters\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-04-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE microwave and wireless technology letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10496584/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"0\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10496584/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 194-GHz Three-Stage Differential Driver Amplifier Utilizing a Three-Element Embedded Core at Near-fmax Frequencies in 65-Nm CMOS
In this letter, we introduce a 194-GHz three-stage differential driver amplifier operating at near-
$f_{\mathrm {max}}$
frequencies. To address practical considerations associated with implementing ON-chip embedding elements within the sub-THz frequency range, we employ a three-element embedded core consisting of three types of embedding networks. This design approach offers greater flexibility in selecting the required embedding elements. Based on the proposed embedded core, a three-stage drive amplifier is implemented in the 65-nm CMOS process. The measurement results indicate that the proposed amplifier exhibits a small signal gain of 20.4 dB, a
$P_{\mathrm {sat}}$
of −2.1 dBm, and a peak PAE of 2.2% at 194 GHz.