通过对溶胶-凝胶生长的高k CeO2层进行后退火来调节铝/CeO2/硅器件的界面质量

IF 2.6 4区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
G. Hari Priya , S.K. Srivastava , M.V. Shankar , K.M.K. Srivatsa , Amish G. Joshi , Koteswara Rao Peta
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引用次数: 0

摘要

针对铝/二氧化铈/硅金属氧化物半导体(MOS)器件,我们全面研究了沉积后退火温度对在 n 型硅(Si)衬底上生长的高 K 氧化铈(CeO2)层的影响及其导致的界面状态。高 K CeO2 薄膜通过旋涂法沉积,并在 400-900 °C 的不同退火温度 (Ta) 下烧结。通过 CV 和 I-V 测量评估了 MOS 器件的固定电荷密度 (Qeff)、层的介电常数 (k)、平带电压 (VFB)、界面缺陷密度 (Dit) 等参数。当温度为 600 ℃ 时,平带偏移的最小值(∼0.05 V)和较低的 Qeff(-4.81 × 1011 C/cm2)均已达到。在 600 °C 的 Ta 温度下,k 和 Dit 分别为 22 和 1.29 × 1012 cm-2。此外,CV 测量显示 600 ℃ 的 Ta 样品具有非常小的滞后和非常低的频率色散。对缺陷态的能量分布进行了评估,发现缺陷态在导带底部最大。紫外光电子能谱(UPS)评估发现,相应 CeO2 层的电子亲和力为 3.29 eV。此外,在 400 °C 的 Ta 温度下退火的样品达到了少数载流子寿命的最大值(147 μs),这表明退火后的温度对溶胶-凝胶工艺沉积的 CeO2 薄膜的性能起着重要作用。因此,本研究证明了溶胶-凝胶法生长的高 k-CeO2 层适用于类似 MOS 器件的可能性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers

Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers

A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO2) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO2/Si metal-oxide-semiconductor (MOS) devices. The high-k CeO2 thin films were deposited by spin-coating and sintered at different annealing temperatures (Ta) in the range of 400–900 °C. The parameters such as fixed charge density (Qeff), dielectric constant (k) of the layers, flat-band voltage (VFB), interface defect density (Dit), etc., of the MOS device were evaluated from CV and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower Qeff (−4.81 × 1011 C/cm2) have been achieved for the Ta of 600 °C. The k and Dit were evaluated to be 22 and 1.29 × 1012 cm−2, respectively at the Ta of 600 °C. In addition, the CV measurements showed a very small hysteresis and very low frequency dispersion for the Ta of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO2 layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at Ta of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO2 films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO2 layers suitable for MOS like devices.

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来源期刊
Microelectronic Engineering
Microelectronic Engineering 工程技术-工程:电子与电气
CiteScore
5.30
自引率
4.30%
发文量
131
审稿时长
29 days
期刊介绍: Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.
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