Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers

A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO₂) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO₂/Si metal-oxide-semiconductor (MOS) devices. The high-k CeO₂ thin films were deposited by spin-coating and sintered at different annealing temperatures (T_a) in the range of 400–900 °C. The parameters such as fixed charge density (Q_eff), dielectric constant (k) of the layers, flat-band voltage (V_FB), interface defect density (D_it), etc., of the MOS device were evaluated from CV and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower Q_eff (−4.81 × 10¹¹ C/cm²) have been achieved for the T_a of 600 °C. The k and D_it were evaluated to be 22 and 1.29 × 10¹² cm⁻², respectively at the T_a of 600 °C. In addition, the CV measurements showed a very small hysteresis and very low frequency dispersion for the T_a of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO₂ layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at T_a of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO₂ films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO₂ layers suitable for MOS like devices.