FPUx：为成本受限的 RISC-V 内核提供高性能浮点支持

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-03-20 DOI:10.1109/TVLSI.2024.3399221

Xian Lin;Heming Liu;Xin Zheng;Huaien Gao;Shuting Cai;Xiaoming Xiong

{"title":"FPUx：为成本受限的 RISC-V 内核提供高性能浮点支持","authors":"Xian Lin;Heming Liu;Xin Zheng;Huaien Gao;Shuting Cai;Xiaoming Xiong","doi":"10.1109/TVLSI.2024.3399221","DOIUrl":null,"url":null,"abstract":"In the Internet of Things (IoT) field, cloud and fog computing dramatically increase the complexity of floating-point (FP) calculations. Cost-constrained microcontrollers (MCUs) urgently need more efficient FP computing methods, such as integrated FP units (FPUs). To this end, this brief proposes FPUx, a high-performance FPU designed through a hybrid pipeline and state-machine approach. The FPUx is integrated into E203 for implementation (E203-FPUx). Furthermore, the Easy-lite is proposed to reduce handshake delay and a range of single-precision FP (FP32) arithmetic IPs are designed to customize FPUs. Compared with E203-FPnew and E203, the performance of E203-FPUx is improved by \n<inline-formula> <tex-math>$1.5\\times $ </tex-math></inline-formula>\n and \n<inline-formula> <tex-math>$36\\times $ </tex-math></inline-formula>\n, and the total energy consumption is saved by 36% and 1430% on average, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores\",\"authors\":\"Xian Lin;Heming Liu;Xin Zheng;Huaien Gao;Shuting Cai;Xiaoming Xiong\",\"doi\":\"10.1109/TVLSI.2024.3399221\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the Internet of Things (IoT) field, cloud and fog computing dramatically increase the complexity of floating-point (FP) calculations. Cost-constrained microcontrollers (MCUs) urgently need more efficient FP computing methods, such as integrated FP units (FPUs). To this end, this brief proposes FPUx, a high-performance FPU designed through a hybrid pipeline and state-machine approach. The FPUx is integrated into E203 for implementation (E203-FPUx). Furthermore, the Easy-lite is proposed to reduce handshake delay and a range of single-precision FP (FP32) arithmetic IPs are designed to customize FPUs. Compared with E203-FPnew and E203, the performance of E203-FPUx is improved by \\n<inline-formula> <tex-math>$1.5\\\\times $ </tex-math></inline-formula>\\n and \\n<inline-formula> <tex-math>$36\\\\times $ </tex-math></inline-formula>\\n, and the total energy consumption is saved by 36% and 1430% on average, respectively.\",\"PeriodicalId\":13425,\"journal\":{\"name\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.8000,\"publicationDate\":\"2024-03-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Very Large Scale Integration (VLSI) Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10535470/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10535470/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

摘要

在物联网（IoT）领域，云计算和雾计算极大地增加了浮点（FP）计算的复杂性。成本有限的微控制器（MCU）迫切需要更高效的 FP 计算方法，如集成 FP 单元（FPU）。为此，本简报提出了 FPUx，一种通过混合流水线和状态机方法设计的高性能 FPU。FPUx 被集成到 E203 中实现（E203-FPUx）。此外，还提出了 Easy-lite 来减少握手延迟，并设计了一系列单精度 FP（FP32）算术 IP 来定制 FPU。与 E203-FPnew 和 E203 相比，E203-FPUx 的性能分别提高了 1.5 美元和 36 美元，总能耗平均分别节省了 36% 和 1430%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores

In the Internet of Things (IoT) field, cloud and fog computing dramatically increase the complexity of floating-point (FP) calculations. Cost-constrained microcontrollers (MCUs) urgently need more efficient FP computing methods, such as integrated FP units (FPUs). To this end, this brief proposes FPUx, a high-performance FPU designed through a hybrid pipeline and state-machine approach. The FPUx is integrated into E203 for implementation (E203-FPUx). Furthermore, the Easy-lite is proposed to reduce handshake delay and a range of single-precision FP (FP32) arithmetic IPs are designed to customize FPUs. Compared with E203-FPnew and E203, the performance of E203-FPUx is improved by

$1.5\times $

and

$36\times $

, and the total energy consumption is saved by 36% and 1430% on average, respectively.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.