Chen-Wei Peng , Chenran He , Hongfan Wu , Si Huang , Cao Yu , Xiaodong Su , Shuai Zou
{"title":"通过低温沉积 i-a-Si:H 反外延缓冲层提高高效硅异质结太阳能电池的性能","authors":"Chen-Wei Peng , Chenran He , Hongfan Wu , Si Huang , Cao Yu , Xiaodong Su , Shuai Zou","doi":"10.1016/j.solmat.2024.112952","DOIUrl":null,"url":null,"abstract":"<div><p>In this work, an effective strategy for realizing high-performance silicon heterojunction (SHJ) solar cells involves replacing the existing rear single intrinsic hydrogenated amorphous silicon (i-a-Si:H) layer by depositing a bi-layer i-a-Si:H stack on the rear side using two different deposition chambers and manipulating the deposition temperature to inhibit epitaxial growth at the interface and maintain a good interfacial passivation effect. A low-temperature procedure is implemented to deposit the first anti-epitaxial i-a-Si:H buffer layer (I1 layer) of ∼1.5 nm thickness with a high hydrogen concentration and a low refractive index prior to the second bulk i-a-Si:H layer (I2 layer) of ∼5.5 nm thickness. The effects of the growth temperature and ignition power during deposition on the optical and structural properties of the i-a-Si:H buffer layers are investigated, and the impact of the buffer layers on carrier transport and collection is also evaluated. Utilizing this strategy, a trade-off between guaranteed passivation capability and low contact resistivity results in an improvement of 0.21%<sub>abs</sub> in power conversion efficiency (PCE), which is mainly driven by increases in V<sub>oc</sub> and FF, and a certified PCE of 25.92 %, with a high open circuit voltage (V<sub>oc</sub>) of 749.7 mV, is achieved on a full-area M6-size industry-grade silicon wafer.</p></div>","PeriodicalId":429,"journal":{"name":"Solar Energy Materials and Solar Cells","volume":null,"pages":null},"PeriodicalIF":6.3000,"publicationDate":"2024-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Improving the performance of high-efficiency silicon heterojunction solar cells through low-temperature deposition of an i-a-Si:H anti-epitaxial buffer layer\",\"authors\":\"Chen-Wei Peng , Chenran He , Hongfan Wu , Si Huang , Cao Yu , Xiaodong Su , Shuai Zou\",\"doi\":\"10.1016/j.solmat.2024.112952\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>In this work, an effective strategy for realizing high-performance silicon heterojunction (SHJ) solar cells involves replacing the existing rear single intrinsic hydrogenated amorphous silicon (i-a-Si:H) layer by depositing a bi-layer i-a-Si:H stack on the rear side using two different deposition chambers and manipulating the deposition temperature to inhibit epitaxial growth at the interface and maintain a good interfacial passivation effect. A low-temperature procedure is implemented to deposit the first anti-epitaxial i-a-Si:H buffer layer (I1 layer) of ∼1.5 nm thickness with a high hydrogen concentration and a low refractive index prior to the second bulk i-a-Si:H layer (I2 layer) of ∼5.5 nm thickness. The effects of the growth temperature and ignition power during deposition on the optical and structural properties of the i-a-Si:H buffer layers are investigated, and the impact of the buffer layers on carrier transport and collection is also evaluated. Utilizing this strategy, a trade-off between guaranteed passivation capability and low contact resistivity results in an improvement of 0.21%<sub>abs</sub> in power conversion efficiency (PCE), which is mainly driven by increases in V<sub>oc</sub> and FF, and a certified PCE of 25.92 %, with a high open circuit voltage (V<sub>oc</sub>) of 749.7 mV, is achieved on a full-area M6-size industry-grade silicon wafer.</p></div>\",\"PeriodicalId\":429,\"journal\":{\"name\":\"Solar Energy Materials and Solar Cells\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":6.3000,\"publicationDate\":\"2024-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solar Energy Materials and Solar Cells\",\"FirstCategoryId\":\"88\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0927024824002642\",\"RegionNum\":2,\"RegionCategory\":\"材料科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENERGY & FUELS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solar Energy Materials and Solar Cells","FirstCategoryId":"88","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0927024824002642","RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENERGY & FUELS","Score":null,"Total":0}
Improving the performance of high-efficiency silicon heterojunction solar cells through low-temperature deposition of an i-a-Si:H anti-epitaxial buffer layer
In this work, an effective strategy for realizing high-performance silicon heterojunction (SHJ) solar cells involves replacing the existing rear single intrinsic hydrogenated amorphous silicon (i-a-Si:H) layer by depositing a bi-layer i-a-Si:H stack on the rear side using two different deposition chambers and manipulating the deposition temperature to inhibit epitaxial growth at the interface and maintain a good interfacial passivation effect. A low-temperature procedure is implemented to deposit the first anti-epitaxial i-a-Si:H buffer layer (I1 layer) of ∼1.5 nm thickness with a high hydrogen concentration and a low refractive index prior to the second bulk i-a-Si:H layer (I2 layer) of ∼5.5 nm thickness. The effects of the growth temperature and ignition power during deposition on the optical and structural properties of the i-a-Si:H buffer layers are investigated, and the impact of the buffer layers on carrier transport and collection is also evaluated. Utilizing this strategy, a trade-off between guaranteed passivation capability and low contact resistivity results in an improvement of 0.21%abs in power conversion efficiency (PCE), which is mainly driven by increases in Voc and FF, and a certified PCE of 25.92 %, with a high open circuit voltage (Voc) of 749.7 mV, is achieved on a full-area M6-size industry-grade silicon wafer.
期刊介绍:
Solar Energy Materials & Solar Cells is intended as a vehicle for the dissemination of research results on materials science and technology related to photovoltaic, photothermal and photoelectrochemical solar energy conversion. Materials science is taken in the broadest possible sense and encompasses physics, chemistry, optics, materials fabrication and analysis for all types of materials.