在 fpga 上实现用于人类检测的猪特征提取的低资源消耗和高速硬件新方法

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-05-15 DOI:10.1016/j.vlsi.2024.102208

Yuhai He , Jiye Huang , Yiming Pan

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引用次数: 0

摘要

在当今日益复杂的交通环境中，行人检测变得越来越重要。定向梯度直方图（HOG）算法已被证明在行人检测中具有很高的效率。本文提出了一种低资源消耗、高速硬件实现的 HOG 算法。在略微牺牲精度的情况下，它提高了计算速度，降低了资源消耗。实验结果表明，该算法实现了每时钟周期 0.933 像素的速度，消耗了 4117 个查找表和 4.5 Kbits 的块 RAM，而其精度在 INRIA 数据集上降低了 1.2%，在麻省理工学院数据集上降低了 0.11%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection

In today’s increasingly complex traffic environment, pedestrian detection has become increasingly important. The Histogram of Oriented Gradients (HOG) algorithm has been proven to be highly efficient in pedestrian detection. This paper proposes a low-resource consumption, high-speed hardware implementation for HOG algorithm. In the case of a slight sacrifice in accuracy, it increases computational speed and reduces resource consumption. Experimental results demonstrate that the implementation achieves a speed of 0.933 pixels per clock cycle and consumes 4117 look-up tables and 4.5 Kbits of block RAMs while its accuracy decreases by 1.2% on the INRIA dataset and by 0.11% on the MIT dataset.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.