(特邀)层状二维栅极电介质中的块状陷阱

Jaemin Shin, Tyafur Pathan, Guanyu Zhou, Christopher L. Hinkle
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引用次数: 0

摘要

在这项工作中,我们合成了新的二维层状电介质,并制作了金属-绝缘体-金属(MIM)电容器,以确定它们在基于过渡金属二卤化物的晶体管中作为按比例栅极电介质(ZrNCl、HfNCl、BiOCl 和 Mg(OH)2)的可行性。虽然成功合成和制造了这些电介质,但电介质的特性在器件应用中明显不尽如人意。在大多数情况下,介电常数仅略微优于二氧化硅(k = 4-6);由于带偏移较差,漏电流过高;最重要的是,正如之前在 III-V 器件中看到的那样,体阱密度非常高。总体而言,目前仍没有适用于按比例场效应晶体管的可行二维栅极电介质。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
(Invited) Bulk Traps in Layered 2D Gate Dielectrics
In this work, we synthesize new 2D layered dielectrics and fabricate metal-insulator-metal (MIM) capacitors to determine their viability for scaled gate dielectrics (ZrNCl, HfNCl, BiOCl, and Mg(OH)2) in transition metal dichalcogenide-based transistors. While successful synthesis and fabrication was demonstrated, the properties of the dielectrics were decidedly underwhelming for device applications. The dielectric constants, in most cases, were only marginally better than SiO2 (k = 4-6), the leakage currents were too high due to poor band offsets, and most importantly, the bulk trap density, as seen previously in III-V devices, was very high. Overall, there still is no viable 2D gate dielectric for scaled field effect transistors.
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