Analysis of interface trap induced ledge in β-Ga2O3 based MOS structures using UV-assisted capacitance–voltage measurements

A ledge feature in the capacitance–voltage (CV) profiles of Ga2O3 MOS (metal–oxide–semiconductor) capacitors is investigated using UV-assisted CV measurements. A model is presented whereby the capacitance ledge is associated with carrier trapping in deep-level states at the Al2O3/Ga2O3 interface. Following UV assisted emptying of interface traps at a constant bias, a voltage ramp toward flatband results in a CV ledge when the trap recombination current becomes equal to the quasi-static sweep charging current. The ledge continues until all the traps below the corresponding pinned surface potential have been filled. Varying the UV energy varies the ledge voltage range and allows a density of states to be determined as a function of energy. A broad interface state peak with maximum density ∼8 × 1012 cm−2 eV−1 for deep trap energies lying between 2.4 and 4.1 eV below the conduction band (CB) edge is extracted. Using the conductance method, the interface trap density is also found to rise toward the CB edge in the range 0.25–0.45 eV below the CB edge, reaching a maximum density of ∼1 × 1012 cm−2 eV−1. Combining these two techniques, an interface trap distribution is estimated for almost the entirety of the bandgap of Ga2O3. This novel technique probes deep interface states where standard methods fail to quantify interface states reliably.