Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency

Previous work has presented a synthesizable design approach to ease the design of an on-chip period-jitter sensor (PJS) with a high resolution. Although the designer of a very large scale integration (VLSI) chip hopes to use this design as an intellectual property (IP), our analysis reveals that this PJS faces key challenges: high power consumption and vulnerability to static PVT and dynamic IR-drop variations. This work develops several design techniques to conquer these challenges at the same time. Taking the PJS IP for monitoring the clock signal in LPDDR4-4266 as a design example, we implement a synthesized 22 nm 2.133 GHz PJS with a resolution of 1.0 ps to verify the design techniques. Post-layout simulation results show that the new design reduces over half of the power while meeting the resolution specification. It passes functional and electrical verification over a broader process variation than the previous design, and the higher variation resiliency assists the synthesizable Verilog code as a soft IP.