A-102 dBm 灵敏度、集成 ADPLL 的多通道异频唤醒接收器

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2024-04-10 DOI:10.1109/OJSSCS.2024.3387388

Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers

{"title":"A-102 dBm 灵敏度、集成 ADPLL 的多通道异频唤醒接收器","authors":"Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers","doi":"10.1109/OJSSCS.2024.3387388","DOIUrl":null,"url":null,"abstract":"This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–\n<inline-formula> <tex-math>$171~\\mu $ </tex-math></inline-formula>\nA range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"43-56"},"PeriodicalIF":0.0000,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496457","citationCount":"0","resultStr":"{\"title\":\"A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL\",\"authors\":\"Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers\",\"doi\":\"10.1109/OJSSCS.2024.3387388\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–\\n<inline-formula> <tex-math>$171~\\\\mu $ </tex-math></inline-formula>\\nA range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.\",\"PeriodicalId\":100633,\"journal\":{\"name\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"volume\":\"4 \",\"pages\":\"43-56\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-04-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496457\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Open Journal of the Solid-State Circuits Society\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10496457/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of the Solid-State Circuits Society","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10496457/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种二进制频移键控（BFSK）外差唤醒接收器（WuRx），在 2.4 GHz 频率下灵敏度为-102-dBm。集成的低功耗全数字锁相环（ADPLL）允许在中频（IF）进行急剧滤波，以提高灵敏度和抗干扰性。通过数据包级负载循环方案，WuRx 在 16 秒至 0.1 秒的延迟时间内实现了 2.2- $171~\mu $ A 的平均电流消耗。此外，它还支持 2.300 至 2.536 GHz 的多达 60 个信道。与载波偏移 3/5/25-MHz 时，信干比（SIR）为 -27/-30/-46 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–

$171~\mu $

A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.

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IEEE Open Journal of the Solid-State Circuits Society

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