利用 ParetoLib 2.0 挖掘扩展信号时态逻辑规范

IF 0.7 4区 计算机科学 Q3 COMPUTER SCIENCE, THEORY & METHODS
Akshay Mambakam, José Ignacio Requeno Jarabo, Alexey Bakhirkin, Nicolas Basset, Thao Dang
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引用次数: 0

摘要

网络物理系统是将物理设备(即传感器和执行器)与软件控制器相结合的复杂环境。这些系统无处不在,其故障带来的危险要求实施各种机制来监控、验证和保证其行为的正确性。本文介绍了 ParetoLib 2.0,这是一款用于离线监控和网络物理系统规范挖掘的 Python 工具。ParetoLib 2.0 使用信号时间逻辑(STL)作为指定时间序列属性的形式主义。ParetoLib 2.0 建立在其他用于评估和挖掘 STL 表达式的工具基础之上,并通过新的功能对其进行了扩展。ParetoLib 2.0 为 STL 跟踪分析实现了一套新的定量运算符、一种新颖的挖掘算法和一个独创的图形用户界面。此外,通过数据类型注释和多核支持,该工具的性能较之前的版本得到了优化。ParetoLib 2.0 可以离线验证 STL 属性,并对参数化 STL 模板进行规范挖掘。由于为 STL 实现了新的定量运算符,该工具的表现力和功能超过了同类运行时监控器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Mining of extended signal temporal logic specifications with ParetoLib 2.0

Mining of extended signal temporal logic specifications with ParetoLib 2.0

Cyber-physical systems are complex environments that combine physical devices (i.e., sensors and actuators) with a software controller. The ubiquity of these systems and dangers associated with their failure require the implementation of mechanisms to monitor, verify and guarantee their correct behaviour. This paper presents ParetoLib 2.0, a Python tool for offline monitoring and specification mining of cyber-physical systems. ParetoLib 2.0 uses signal temporal logic (STL) as the formalism for specifying properties on time series. ParetoLib 2.0 builds upon other tools for evaluating and mining STL expressions, and extends them with new functionalities. ParetoLib 2.0 implements a set of new quantitative operators for trace analysis in STL, a novel mining algorithm and an original graphical user interface. Additionally, the performance is optimised with respect to previous releases of the tool via data-type annotations and multi core support. ParetoLib 2.0 allows the offline verification of STL properties as well as the specification mining of parametric STL templates. Thanks to the implementation of the new quantitative operators for STL, the tool outperforms the expressiveness and capabilities of similar runtime monitors.

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来源期刊
Formal Methods in System Design
Formal Methods in System Design 工程技术-计算机:理论方法
CiteScore
2.00
自引率
12.50%
发文量
16
审稿时长
>12 weeks
期刊介绍: The focus of this journal is on formal methods for designing, implementing, and validating the correctness of hardware (VLSI) and software systems. The stimulus for starting a journal with this goal came from both academia and industry. In both areas, interest in the use of formal methods has increased rapidly during the past few years. The enormous cost and time required to validate new designs has led to the realization that more powerful techniques must be developed. A number of techniques and tools are currently being devised for improving the reliability, and robustness of complex hardware and software systems. While the boundary between the (sub)components of a system that are cast in hardware, firmware, or software continues to blur, the relevant design disciplines and formal methods are maturing rapidly. Consequently, an important (and useful) collection of commonly applicable formal methods are expected to emerge that will strongly influence future design environments and design methods.
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