设计新型低成本三节点嵌入式可自动恢复加固闩锁

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-04-24 DOI:10.1016/j.vlsi.2024.102199

Hui Xu , Shuo Zhu , Ruijun Ma , Zhengfeng Huang , Huaguo Liang , Haojie Sun , Chaoming Liu

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引用次数: 0

摘要

随着晶体管特性的降低，尤其是在辐射环境中，CMOS 器件受三重节点重置的影响越来越大。针对现有辐射加固设计的高开销和高延迟等缺点，本文提出了一种新型低成本三节点重置自恢复锁存器。仿真结果表明，与现有的三节点上集加固设计相比，所提出的锁存器在功耗、延迟和功率-延迟乘积方面分别降低了 34.57%、6.42% 和 34.98%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of novel low cost triple-node-upset self-recoverable hardened latch

CMOS devices are increasingly affected by triple-node-upset as transistor characteristics reduce, particularly in radiation environments. For the shortcomings of the existing radiation hardened designs, including high overhead and high delay, this paper proposes a novel low cost triple-node-upset self-recoverable latch. Simulation results show that compared with the existing triple-node-upset hardened designs, the proposed latch has reduced power consumption, delay, and power-delay product by 34.57 %, 6.42 %, and 34.98 %, respectively.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.