A scalable top-gate graphene field effect transistor with a polydimethylsiloxane dielectric

The limitations of modern CMOS technology have created a call to action for novel devices with great scalability potential. Graphene has been recognized as a suitable material for an enhanced transistor channel based on its incredibly large conductivity while also being easily scaled. Previous research has noted the importance of a top gate device structure, which is difficult to accomplish for graphene transistors due to graphene's incompatibility with oxide growth processes. A novel process flow for graphene field effect transistors with scalability is presented. The emphasis is on the growth of multilayer graphene using chemical vapor deposition and the implementation of polydimethylsiloxane as a gate dielectric. Polydimethylsiloxane gate insulator thickness of 815 nm and 570 nm were successfully developed on 4in large-scale wafers. Two devices of similar channel dimensions and different dielectric were compared and mobilities of 14.57cm²V⁻¹s⁻¹ and 0.44 cm²V⁻¹s⁻¹ were measured. Gate voltage sweeps from -20 V to 20 V also demonstrated channel current modulation with a charge neutrality point between 5 V and 8 V, indicating achievement of expected device operation.