用于三维堆叠集成电路的新型裸片级灵活设计测试架构

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-03-26 DOI:10.1016/j.vlsi.2024.102190

Qingping Zhang , Wenfa Zhan , Xiaoqing Wen

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引用次数: 0

摘要

针对三维堆叠集成电路提出了一种芯片级设计测试架构。该架构的主要组成部分是新提出的可配置边界单元，在此基础上实现了灵活的并行测试。并行扫描链的数量和长度均可在测试过程中进行配置。该测试架构具有重量轻、并行测试配置灵活性高、模块化和兼容 IEEE P1149.1 等特点。在这项工作中，对基础架构和实施方面进行了说明。实验结果表明了所需的测试加速度。当测试矢量数量超过 300 个时，加速比大约达到极限，等于并行扫描链的数量。

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A new die-level flexible design-for-test architecture for 3D stacked ICs

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.