基于尖峰神经 P 系统的新型 GF(p) 紧凑型有限域算术电路,可在低成本 FPGA 中按要求实现通信

IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
José L. I. Rangel;Moises I. Arroyo;Eduardo Vázquez;Juan G. Avalos;Giovanny Sanchez
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引用次数: 0

摘要

有限场算术运算对于计算侧信道攻击、身份验证和数字签名等尖端应用中使用的复杂密码学算法至关重要。目前,这些算法的仿真超出了传统计算系统的计算能力。特别是当这些算法在资源有限的电子设备中实施时,这一点就变得尤为重要。特别是,要提高这些设备的执行时间,通常需要更多的面积。为了解决这个问题,大量工作都集中在开发 GF(p)上的紧凑型传统二进制有限域算术电路上,因为这些电路需要消耗大量面积。受神经现象的启发,计算机科学的一个新兴分支为改善传统算术电路的面积消耗做出了巨大努力。然而,开发 GF(p)上的紧凑有限域算术电路仍是一项具有挑战性的任务。在这封信中,我们首次提出了基于尖峰神经 P(SN P)系统的四种新的 GF(p)有限场算术电路的设计,并根据要求进行了通信。此外,我们还提出了一种神经处理器,通过使用同一个处理核心来执行 GF(p) 上的四种新有限场算术运算,这在使用传统二进制电路时是不可行的,因为 GF(p) 上的每个有限场算术-二进制电路都是单独实现的,从而显著改善了面积消耗。这主要是因为神经处理器可以动态地改变其配置,而配置是根据每个神经元的连接和点燃规则来定义的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
New Compact Finite-Field Arithmetic Circuits Over GF(p) Based on Spiking Neural P Systems With Communication on Request Implemented in a Low-Cost FPGA
Finite-field arithmetic operations are vital for the computation of complex cryptography algorithms used in several cutting-edge applications, such as side-channel attacks, authentication, and digital signatures, among others. Currently, the simulation of these algorithms exceeds the computational capabilities of conventional computing systems. This aspect becomes critical, especially when these algorithms are implemented in resource-constrained electronic appliances. In particular, the improvement of execution time in these devices generally require more area. To overcome this issue, a large number of works have been focused on the development of compact conventional binary finite-field arithmetic circuits over GF(p) since these demand a large area consumption. Inspired by neural phenomena, a new emerging branch of computer science has made intensive efforts to improve area consumption of conventional arithmetic circuits. However, the development of compact finite-field arithmetic circuits over GF(p) is a still a challenging task. In this letter, we present for the first time, the design of four new finite-field arithmetic circuits over GF(p) based on spiking neural P (SN P) systems with communication on request. In addition, we propose a neural processor to perform four new finite-field arithmetic operations over GF(p) by using the same processing core, which is not feasible with the use of conventional binary circuits since each finite-field arithmetic-binary circuit over GF(p) is implemented separately, to significantly improve the area consumption. This has mainly been achieved since the neural processor dynamically change its configuration, which is defined in terms of the connectivity and firing rules of each neuron.
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来源期刊
IEEE Embedded Systems Letters
IEEE Embedded Systems Letters Engineering-Control and Systems Engineering
CiteScore
3.30
自引率
0.00%
发文量
65
期刊介绍: The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.
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