地址扩展:细粒度线程安全元数据管理的架构支持

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Deepanjali Mishra;Konstantinos Kanellopoulos;Ashish Panwar;Akshitha Sriraman;Vivek Seshadri;Onur Mutlu;Todd C. Mowry
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引用次数: 0

摘要

近几十年来,软件系统的规模和复杂性都有了显著增长。因此,这些系统更容易出现错误,从而导致性能和正确性方面的挑战。使用运行时监控工具是缓解这些挑战的一种方法。然而,这些工具需要为其监控的每个字节的应用数据维护元数据,这就会因额外的元数据访问而产生性能开销。我们提出了 "地址扩展"(Address Scaling)这一新的硬件框架,该框架可执行细粒度元数据管理,以减少运行时监控工具的元数据访问开销。我们的机制基于对不同运行时监控工具以不同粒度维护元数据的观察。我们的主要见解是在同一缓存行中维护数据及其相应的元数据,以保持本地性。与将元数据存储在与数据分离的内存区域的最先进系统相比,在顺序和随机内存访问模式下,地址缩放可分别提高 Memcheck(一种检测内存相关错误的动态监控工具)的性能 3.55 倍和 6.58 倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management
In recent decades, software systems have grown significantly in size and complexity. As a result, such systems are more prone to bugs which can cause performance and correctness challenges. Using run-time monitoring tools is one approach to mitigate these challenges. However, these tools maintain metadata for every byte of application data they monitor, which precipitates performance overheads from additional metadata accesses. We propose Address Scaling , a new hardware framework that performs fine-grained metadata management to reduce metadata access overheads in run-time monitoring tools. Our mechanism is based on the observation that different run-time monitoring tools maintain metadata at varied granularities. Our key insight is to maintain the data and its corresponding metadata within the same cache line, to preserve locality. Address Scaling improves the performance of Memcheck , a dynamic monitoring tool that detects memory-related errors, by 3.55× and 6.58× for sequential and random memory access patterns respectively, compared to the state-of-the-art systems that store the metadata in a memory region that is separate from the data.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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