利用 Racetrack 内存对长 DNA 读数进行预配准过滤的高效内存布局

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Asif Ali Khan;Fazal Hameed;Taha Shahroodi;Alex K. Jones;Jeronimo Castrillon
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引用次数: 0

摘要

DNA 序列比对是生物信息学中一项基本且计算成本高昂的操作。研究人员开发了预配准过滤器,通过丢弃匹配度较低的位置,有效减少配准过程中消耗的数据量。然而,过滤操作本身需要大量内存,传统的 Von-Neumann 架构在这方面表现不佳。因此,最近的设计提倡使用基于堆叠 DRAM 的计算近存储器(CNM)加速器和更奇特的存储器技术,如赛道存储器(RTM)。然而,这些设计只能支持约 100 个核苷酸的小 DNA 读取,即短读取。这封信提出了一种同时处理长读和短读的 CNM 系统。它引入了一种新颖的数据置放解决方案,大大提高了并行性并减少了开销。评估结果表明,与最先进的系统相比,该系统的执行时间(1.32 美元/次)和能耗(50%)大幅减少。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory
DNA sequence alignment is a fundamental and computationally expensive operation in bioinformatics. Researchers have developed pre-alignment filters that effectively reduce the amount of data consumed by the alignment process by discarding locations that result in a poor match. However, the filtering operation itself is memory-intensive for which the conventional Von-Neumann architectures perform poorly. Therefore, recent designs advocate compute near memory (CNM) accelerators based on stacked DRAM and more exotic memory technologies such as racetrack memories (RTM). However, these designs only support small DNA reads of circa 100 nucleotides, referred to as short reads . This letter proposes a CNM system for handling both long and short reads. It introduces a novel data-placement solution that significantly increases parallelism and reduces overhead. Evaluation results show substantial reductions in execution time ( $1.32\times$ ) and energy consumption (50%), compared to the state-of-the-art.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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