灵长类动物为网络应用自动生成软处理器的框架

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-01-26 DOI:10.1109/LCA.2024.3358839

Rui Ma;Jia-Ching Hsu;Ali Mansoorshahi;Joseph Garvey;Michael Kinsner;Deshanand Singh;Derek Chiou

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引用次数: 0

摘要

FPGA 上的叠加处理器可实现：i) 通过调用库函数的顺序代码实现软件可编程性；ii) 通过将库调用转换为调用相应的加速器实现高性能；iii) 比重新编程 FPGA 更快地部署。传统上，覆盖层是用 RTL 手写的，并通过手写汇编进行编程。我们提出了 Primate 框架，它能从以注释 C++ 编写的应用程序中自动生成覆盖层。我们在 Whippersnapper（Dang 等人，2017 年）P4 基准上对 Primate 进行了评估。与高性能 CPU 解决方案 PISCES（Shahbaz 等人，2016 年）相比，Primate Overlay 的延迟为 0.06x - 0.15x；与 FPGA 上的 P4 HLS 编译器 P4FPGA（Wang 等人，2017 年）生成的解决方案相比，Primate Overlay 的延迟为 0.25x - 2.3x。

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Primate: A Framework to Automatically Generate Soft Processors for Network Applications

Overlay processors on FPGAs enable i) software programmability through sequential code calling library functions, ii) high performance by converting the library calls to invocations of corresponding accelerators, and iii) faster deployment than reprogramming the FPGA. Traditionally, overlays have been hand-written in RTL and programmed through handwritten assembly. We present the Primate framework, which automatically generates overlays from applications written in annotated C++. We evaluated Primate on Whippersnapper (Dang et al. 2017) P4 benchmarks. Primate Overlay latencies are 0.06x - 0.15x compared to PISCES (Shahbaz et al. 2016), a high-performance CPU solution, and 0.25x - 2.3x compared to solutions generated by P4FPGA (Wang et al. 2017), a P4 HLS compiler on FPGA.

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.