具有单抽头推测式 DFE 和宽频率捕获范围的 16 Gb/s 波特率 CDR 电路

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-01-25 DOI:10.1109/TVLSI.2024.3353197

Po-Yuan Chou;Wei-Ming Chen;Shen-Iuan Liu

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引用次数: 0

摘要

本文介绍了一种具有单抽头决策反馈均衡器（DFE）和宽频率捕获范围（FCR）的 16 Gb/s 波特率时钟和数据恢复（CDR）电路。所提出的基于非对称模式的相位检测器用于实现较宽的 FCR。该四分之一速率 CDR 电路采用 40 纳米 CMOS 技术制造，有效面积为 0.1094 mm2。对于 27-1 的 16 Gb/s PRBS，CDR 电路的功率为 38.4 mW，其计算能效为 2.4 pJ/b。测量的 FCR 为 40.6%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range

A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm2. For a 16 Gb/s PRBS of 27–1, the power of the CDR circuit is 38.4 mW and its calculated energy efficiency is 2.4 pJ/b. The measured FCR is 40.6%.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.