基于负电容场效应晶体管的双分路控制 6 T-SRAM 单元设计,适用于高能效和稳健的计算型内存架构

IF 2.6 4区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Birudu Venu, Tirumalarao Kadiyam, Koteswararao Penumalli, Sivasankar Yellampalli, Ramesh Vaddi
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引用次数: 0

摘要

我们设计并探索了一种基于负电容场效应晶体管(NCFET)的双分割控制(DSC)6T-SRAM 单元,该单元采用内存中计算(CiM)架构,用于高效演示深度神经网络(DNN)的基本操作,如输入-重量(Dot)乘积。在 0.3 V 和 0.5 V 电源电压下,分析了铁电层厚度 (Tfe) 对 SRAM 单元性能指标的影响,如读取噪声余量 (RNM)、写入噪声余量 (WNM) 以及读写操作的能效。结果表明,由于具有陡坡特性,基于 NCFET 的 DSC 6T-SRAM 单元设计与基线 CMOS DSC SRAM 单元设计相比,在 VDD = 0.3 V 和 0.5 V 条件下(Tfe 范围为 1 nm 至 3 nm),分别表现出更好的 RM、WM 和能效。此外,与 NCFET 6 T-SRAM 单元设计相比,NCFET 6 T-SRAM 单元的 NCFET 双分割控制方案在提高能效的同时,还改善了读取稳定性和写入能力。在 VDD = 0.3 V 和 0.5 V 条件下,基于 NCFET 的 DSC 6T-SRAM CiM 单元设计的能耗分别比同等基线 40 nm CMOS/基线 SRAM CiM 设计低 22.77 倍和 12.41 倍,比基于 NCFET 的 SRAM CiM 低 25.80 倍和 22.76 倍。在最佳Tfe值下,NCFET具有更好的陡峭阈下斜率特性,与基线CMOS设计相比,基于NCFET的SRAM CiM电路有望具有更高的噪声裕度和更低的能耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

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来源期刊
Microelectronic Engineering
Microelectronic Engineering 工程技术-工程:电子与电气
CiteScore
5.30
自引率
4.30%
发文量
131
审稿时长
29 days
期刊介绍: Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.
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