具有动态 EOV 消除和预测性混合信号阻抗增强功能的 0.00179 mm2/Ch 斩波稳定 TDMA 神经记录系统。

Nader Sherif Kassem Fathy;Ritwik Vatsyayan;Andrew M. Bourhis;Shadi A. Dayeh;Patrick P. Mercier
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引用次数: 0

摘要

本文介绍了一种数字辅助多通道神经记录系统。该系统采用 16 通道斩波稳定时分多址(TDMA)方案,将多路神经信号记录到单个共享模拟前端(AFE)中。在局部场电位(LFP)和动作电位(AP)频段,斩波器将整个调制频谱的总综合噪声分别降低了 2.4 倍和 4.3 倍。此外,基于 Sign-Sign 最小均方差(LMS)自适应滤波器(AF)的新型阻抗增强器可预测输入信号并对交流耦合电容器进行预充电。阻抗增压器模块将 AFE 输入阻抗提高了 39 倍,而面积只增加了 7.1%。拟议的系统省去了从多路复用神经信号中提取电极偏移电压(EOV)通常所需的片上数字解调、滤波和重调制,从而使 EOV 滤波器模块的面积和功耗分别节省了 3.6 倍和 2.8 倍。Sign-Sign LMS AF 被重新用于确定系统环路增益,从而放宽了对反馈 DAC 精度的要求,与传统的过采样 DAC 截断误差 ΔΣ 调制器相比,可节省 10.1 倍的功耗。拟议的 SoC 采用 65 纳米 CMOS 设计和制造,每个通道占用 0.00179 平方毫米的有效面积。每个通道的功耗为 5.11 μW,同时在 AP 和 LFP 波段实现了 2.19 μVrms 和 2.4 μVrms 的输入参考噪声 (IRN)。由此产生的 AP 波段噪声效率系数 (NEF) 为 1.8。使用基于对二甲苯 C 的薄膜铂纳米棒微电极对 Sprague-Dawley 大鼠进行急性体内记录,验证了所提出的系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 0.00179 mm2/Ch Chopper-Stabilized TDMA Neural Recording System With Dynamic EOV Cancellation and Predictive Mixed-Signal Impedance Boosting
This article presents a digitally-assisted multi-channel neural recording system. The system uses a 16-channel chopper-stabilized Time Division Multiple Access (TDMA) scheme to record multiplexed neural signals into a single shared analog front end (AFE). The choppers reduce the total integrated noise across the modulated spectrum by 2.4 $ \times $ and 4.3 $ \times $ in Local Field Potential (LFP) and Action Potential (AP) bands, respectively. In addition, a novel impedance booster based on Sign-Sign least mean squares (LMS) adaptive filter (AF) predicts the input signal and pre-charges the AC-coupling capacitors. The impedance booster module increases the AFE input impedance by a factor of 39 $ \times $ with a 7.1% increase in area. The proposed system obviates the need for on-chip digital demodulation, filtering, and remodulation normally required to extract Electrode Offset Voltages (EOV) from multiplexed neural signals, thereby achieving 3.6 $ \times $ and 2.8 $ \times $ savings in both area and power, respectively, in the EOV filter module. The Sign-Sign LMS AF is reused to determine the system loop gain, which relaxes the feedback DAC accuracy requirements and saves 10.1 $ \times $ in power compared to conventional oversampled DAC truncation-error ΔΣ-modulator. The proposed SoC is designed and fabricated in 65 nm CMOS, and each channel occupies 0.00179 mm 2 of active area. Each channel consumes 5.11 μW of power while achieving 2.19 μV rms and 2.4 μV rms of input referred noise (IRN) over AP and LFP bands. The resulting AP band noise efficiency factor (NEF) is 1.8. The proposed system is verified with acute in-vivo recordings in a Sprague-Dawley rat using parylene C based thin-film platinum nanorod microelectrodes.
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