{"title":"基于全变频器的 12.5 Gb/s 1.38 mW 光接收器，带多级反馈 TIA 和连续时间线性均衡器","authors":"Peng Yan, Chaerin Hong, Po-Hsuan Chang, Hyungryul Kang, Dedeepya Annabattuni, Ankur Kumar, Yang-Hang Fan, Ruida Liu, Ramy Rady, Samuel Palermo","doi":"10.1007/s10470-024-02248-1","DOIUrl":null,"url":null,"abstract":"<div><p>An optical receiver employs an all-inverter-based front-end design that provides maximum transconductance for a given power supply and allows for ultra-low power consumption. The feedback transimpedance amplifier (TIA) input stage utilizes a multi-stage amplifier to achieve a dramatic increase in feedback resistance and lower input-referred noise. Cascading an inverter-based active inductor continuous-time linear equalizer provides frequency peaking to compensate the input stage TIA that is intentionally designed with a reduced bandwidth to achieve adequate sensitivity at low power. Fabricated in 28 nm CMOS, the 12.5 Gb/s optical receiver achieves <span>\\(-\\)</span>10.7 dBm OMA sensitivity at 0.11 pJ/bit energy efficiency and occupies only 720 <span>\\(\\upmu \\text {m}^{2}\\)</span> area.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2000,"publicationDate":"2024-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer\",\"authors\":\"Peng Yan, Chaerin Hong, Po-Hsuan Chang, Hyungryul Kang, Dedeepya Annabattuni, Ankur Kumar, Yang-Hang Fan, Ruida Liu, Ramy Rady, Samuel Palermo\",\"doi\":\"10.1007/s10470-024-02248-1\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>An optical receiver employs an all-inverter-based front-end design that provides maximum transconductance for a given power supply and allows for ultra-low power consumption. The feedback transimpedance amplifier (TIA) input stage utilizes a multi-stage amplifier to achieve a dramatic increase in feedback resistance and lower input-referred noise. Cascading an inverter-based active inductor continuous-time linear equalizer provides frequency peaking to compensate the input stage TIA that is intentionally designed with a reduced bandwidth to achieve adequate sensitivity at low power. Fabricated in 28 nm CMOS, the 12.5 Gb/s optical receiver achieves <span>\\\\(-\\\\)</span>10.7 dBm OMA sensitivity at 0.11 pJ/bit energy efficiency and occupies only 720 <span>\\\\(\\\\upmu \\\\text {m}^{2}\\\\)</span> area.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.2000,\"publicationDate\":\"2024-02-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-024-02248-1\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-024-02248-1","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer
An optical receiver employs an all-inverter-based front-end design that provides maximum transconductance for a given power supply and allows for ultra-low power consumption. The feedback transimpedance amplifier (TIA) input stage utilizes a multi-stage amplifier to achieve a dramatic increase in feedback resistance and lower input-referred noise. Cascading an inverter-based active inductor continuous-time linear equalizer provides frequency peaking to compensate the input stage TIA that is intentionally designed with a reduced bandwidth to achieve adequate sensitivity at low power. Fabricated in 28 nm CMOS, the 12.5 Gb/s optical receiver achieves \(-\)10.7 dBm OMA sensitivity at 0.11 pJ/bit energy efficiency and occupies only 720 \(\upmu \text {m}^{2}\) area.
期刊介绍：
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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