High-efficiency CMOS charge pump for ultra-low power RF energy harvesting applications

This paper explicates the design and implementation of a switch capacitor DC–DC converter system for Radio Frequency (RF) energy harvesting applications for an input voltage in the sub-150 mV range, using 180-nm CMOS triple-well BCD technology. The proposed system incorporates a charge pump architecture that employs an improvised Dynamic Gate Biasing (DGB), Forward and Reverse Body Bias technique (FRBB), along with a time axis symmetrical clocking scheme implemented using an advanced bootstrapped CMOS driver to enhance the overall drive capability of the system at low input voltages. Post-layout extracted simulations demonstrate that the proposed system achieves higher overall efficiency, delivering a peak Power Conversion Efficiency (PCE) of 85.8% at 125 mV input voltage, outperforming other state-of-the-art architectures in similar voltage ranges. Moreover, the proposed system exhibits reliable operation even at input voltages as low as 85 mV, while maintaining good overall efficiency.