用于 5G 应用的 18-28 GHz 双模下变频集成电路

IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Saeed Naghavi, Kaisa Ryynänen, Mahwish Zahra, Aleksi Korsman, Kari Stadius, Marko Kosunen, Vishnu Unnikrishnan, Lauri Anttila, Mikko Valkama, Jussi Ryynänen
{"title":"用于 5G 应用的 18-28 GHz 双模下变频集成电路","authors":"Saeed Naghavi,&nbsp;Kaisa Ryynänen,&nbsp;Mahwish Zahra,&nbsp;Aleksi Korsman,&nbsp;Kari Stadius,&nbsp;Marko Kosunen,&nbsp;Vishnu Unnikrishnan,&nbsp;Lauri Anttila,&nbsp;Mikko Valkama,&nbsp;Jussi Ryynänen","doi":"10.1007/s10470-023-02232-1","DOIUrl":null,"url":null,"abstract":"<div><p>Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 <span>\\(\\text {mm}^\\text {2}\\)</span>. The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2000,"publicationDate":"2024-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-023-02232-1.pdf","citationCount":"0","resultStr":"{\"title\":\"An 18–28 GHz dual-mode down-converter IC for 5G applications\",\"authors\":\"Saeed Naghavi,&nbsp;Kaisa Ryynänen,&nbsp;Mahwish Zahra,&nbsp;Aleksi Korsman,&nbsp;Kari Stadius,&nbsp;Marko Kosunen,&nbsp;Vishnu Unnikrishnan,&nbsp;Lauri Anttila,&nbsp;Mikko Valkama,&nbsp;Jussi Ryynänen\",\"doi\":\"10.1007/s10470-023-02232-1\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 <span>\\\\(\\\\text {mm}^\\\\text {2}\\\\)</span>. The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.2000,\"publicationDate\":\"2024-01-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://link.springer.com/content/pdf/10.1007/s10470-023-02232-1.pdf\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-023-02232-1\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-023-02232-1","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

新出现的频谱趋势要求对 5G 新无线电频率范围 1(FR1)和频率范围 2(FR2)频段进行更高的整合,以提高频谱可用性和频谱共享机会。为了在一个无缝硬件实体中同时接收 FR1 和 FR2 频段,我们建议将同频和异频架构结合起来。这就需要加入一个下变频模块,将接收到的 FR2 波段信号下传至 FR1 波段,确保与 FR1 直接转换接收器(DCR)兼容,以实现最终信号接收。本文的主要重点是设计和实现所需的集成下变频器。该模块包括一个集成平衡器、一个具有旁路模式的低噪声放大器(LNA)、一个双模混频器和一个中频(IF)放大器。与标称模式相比,旁路模式有助于进一步提高线性度性能。旁路模式设计用于联合通信和传感操作,以避免接收器的压缩。这项研究还采用混合信号方法,在本地振荡器(LO)信号分配网络中加入了相位调谐元件。电路采用 22 纳米 CMOS 工艺实现,有源芯片面积为 0.6(text {mm}^text {2}\)。测量结果表明,所实现的芯片可以在 18-28 GHz 的宽频率范围内高效地完成所需的频率转换。转换增益为 4.5-7.5 dB,噪声系数为 15-19.7 dB,1 dB 压缩点 (IP1dB) 为 - 16 至 - 10 dBm,输入三阶截取点 (IIP3) 为 - 5 至 0 dBm。旁路模式的 IP1 dB 和 IIP3 测量值分别为 +0.5 至 +4.5 dBm 和 +8.5 至 +10 dBm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

An 18–28 GHz dual-mode down-converter IC for 5G applications

An 18–28 GHz dual-mode down-converter IC for 5G applications

Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 \(\text {mm}^\text {2}\). The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.

求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信