A low power arithmetic unit driven motion estimation and intra prediction accelerators with adaptive Golomb–Rice entropy encoder for H.264 encoders on FPGA

In the recent era, the utilization of the H.264 encoder has been increasing due to its outstanding performance in video compression. However, compressing video with reduced power is still a challenging issue faced by H.264 encoders. Thus, the proposed study intends to minimize the power consumption of H.264 encoders on FPGA by optimizing the basic components of H.264, thereby enhancing performance. For this purpose, the elements like Motion Estimation, intra-prediction, transform unit and entropy encoder are optimized through the effective schemes introduced in the proposed work. Initially, the Motion Estimation unit can be alternated by optimizing the fundamental components of Block Matching Algorithms. To design the Block Matching Algorithms, the proposed study introduces low-power arithmetic units like an add-one circuit-based Carry SeLect Adder and Sum of Absolute Difference. With the help of these methods, the Block Matching Algorithms has designed, and the Motion Estimation Unit can be effectively optimized. Then, by adopting a comparator-less reusing method, the intra-prediction unit is optimized. Next, the transform unit is optimized by proposing a Steerable Discrete Cosine Transform and finally, the entropy encoders are optimized by combining Golomb and Rice entropy encoders. The proposed study uses the schemes above to improve the efficiency of H.264 encoders on FPGA. The experimental analysis in the proposed study is done using Xilinx software. The simulation results show that the proposed work obtained higher power, LUTs, delay, PSNR, frequency and MSE than other competing methods.