Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband

The digital integrated circuit (IC) testing model module is applied in this study to simulate the fabrication and testing of integrated circuits. The yield and quality of ICs are analyzed by assuming that the wafer devices under test conditions are normal probability distributions. The difficulties of testing and verification become increasingly great as the design function of the chip becomes remarkably complex. Conversely, the automotive industry chip supply chain has been substantially affected since the COVID-19 outbreak. The shortage of chips in the auto-market has always existed; therefore, increasing available chips under a limited production capacity has become a top priority. Therefore, this study applies the digital integrated circuit testing model (DITM) and proposes a retest plan. This method does not require considerable time to collect large wafer data, nor does it require additional hardware equipment. Furthermore, the required test quality parameters are set, and the test is repeated on the device by adjusting the test guardband (TGB). Moreover, three retesting schemes are proposed to improve the IC test quality (Yq) and test yield (Yt) to meet the requirements of consumers for product quality. A set of 2021 IEEE International Roadmap for Devices and Systems (IRDS) parameters is used to demonstrate the three proposed retesting schemes. The simulation results from the 2021 IRDS data prove that the retest method can effectively improve the test yield (Yt). A comparison of the estimated results of the three retest methods shows that using the repeat test method can maximize the test yield without sacrificing the test quality (Yq). By contrast, repeat testing can indeed improve the test yield (Yt) by 14% or more. Moreover, the increase in sellable ICs not only increases additional earnings for corporations, but also alleviates the current global shortage of automotive ICs.