郁金香免转低功耗片上网络

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Atiyeh Gheibi-Fetrat;Negar Akbarzadeh;Shaahin Hessabi;Hamid Sarbazi-Azad
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引用次数: 0

摘要

半导体行业取得了重大技术进步,导致片上系统(SoC)中的处理内核数量不断增加。为了促进众多片上内核之间的通信,采用了片上网络(NoC)。设计 NoC 的主要挑战之一是功耗管理,因为 NoC 消耗了 SoC 总功耗的很大一部分。在 NoC 的功耗密集型组件中,路由器尤为突出。我们发现,路由器中负责在网状拓扑中实现转向的一些功耗密集型组件与其他组件相比利用率较低。因此,我们提出了无转向低功耗网络芯片 Tulip,通过从路由器结构中移除相应的组件来避免路由器内部的转向。在转弯时(例如,在当前维度的末端),Tulip 会强制弹出数据包,然后将其重新弹入下一维度通道(即沿下一维度路径的起点)。由于其无死锁特性,Tulip 方案可与任何确定性、部分自适应和全自适应路由算法正交使用,并可轻松扩展到任何 n 维网格拓扑。我们的分析表明,对于 2D-5D 网状路由器,Tulip 可以将静态功耗和面积分别降低 24%-50% 和 25%-55%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Tulip: Turn-Free Low-Power Network-on-Chip
The semiconductor industry has seen significant technological advancements, leading to an increase in the number of processing cores in a system-on-chip (SoC). To facilitate communication among the numerous on-chip cores, a network-on-chip (NoC) is employed. One of the main challenges of designing NoCs is power management since the NoC consumes a significant portion of the total power of the SoC. Among the power-intensive components of the NoC, routers stand out. We observe that some power-intensive components of routers, responsible for implementing turn in the mesh topology, are underutilized compared to others. Therefore, we propose Tulip, a turn-free low-power network-in-chip, that avoids within-router turns by removing the corresponding components from the router structure. On a turn (e.g., at the end of the current dimension), Tulip forces the packet to be ejected and then reinjects it to the next dimension channel (i.e., the beginning of the path along the next dimension). Due to its deadlock-free nature, Tulip's scheme may be used orthogonally with any deterministic, partially-adaptive, and fully-adaptive routing algorithms, and can easily be extended for any n-dimensional mesh topology. Our analysis reveals that Tulip can reduce the static power and area by 24%−50% and 25%-55%, respectively, for 2D-5D mesh routers.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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