使用基于 LCSLA 的双字段吠陀乘法器实现高能效 ECC

Senthil Sengottaiyan, Vadivel Subramaniam, Yuvaraja Thangavel, Karthick Sekar
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引用次数: 0

摘要

椭圆曲线加密(ECC)技术用于安全标准,如安全密钥管理(SKM)、数字签名、数据认证等。通过统一设计,ECC 技术能够进行顺序和并行模式处理。它同样适用于密码系统的二进制域和素数域。DMM 结构是利用 CSA 开发的。这种加法器需要更多的全加法器电路,占用更多的面积。为了克服这一问题,本文讨论了四种不同的方法,如 DMM 优化进位前瞻加法器、DMM 优化进位旁路加法器、DMM-查找表进位选择加法器和双字段吠陀乘法器 - LCSLA,用于提高 ECC 的性能。分析了功率利用率、时间延迟信息和硬件面积开销等参数,并与现有方法进行了比较。在这四种方法中,DVM-LCSLA 方法在 FPGA 和 ASIC 性能方面取得了更好的结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Power Efficient Implementation of ECC Using LCSLA Based Dual Field Vedic Multiplier
The Elliptic Curve Cryptographic (ECC) technique is employed for security standards such as Security Key Management (SKM), digital signature, data authentication and so on. The ECC technique is capable of sequential and parallel mode processes through a unified design. It is used for both equally binary fields and prime fields of cryptosystems. The DMM structure has been developed using CSA. This adder requires a greater amount of Full Adder circuits, which occupy more area. To overcome this problem, this paper discusses four different methods, such as DMM-Optimized Carry Look Ahead Adder, DMM-Optimized Carry Bypass Adder, DMM-Look up Table Carry Select Adder, and Dual Field Vedic Multiplier – LCSLA, which is used to increase the performance of the ECC. The parameters like power utilization, time delay information, and hardware area overhead are analyzed and compared with existing methods. Among those four methods, the DVM-LCSLA method gave better results in FPGA and ASIC performances.
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