RFSoC-FPGA Realization of a Code-Multiplexed Digital Receiver (CMDR) Using 1-ADC/Quad-Channel

A 4-channel code-multiplexed digital receiver is presented for multiple-input-multiple-output (MIMO) applications targeting 5G millimeter-wave (mm-Wave) communications. The receiver employs a code-multiplexing (CM) topology where multiple channels are encoded with unique orthogonal Walsh-Hadamard codes and multiplexed into a single-channel for digitization. This approach overcomes the bottleneck of hardware complexity, cost, and power consumption in traditional multiplexing topologies by employing a single wideband analog-to-digital converter (ADC) to serve several channels. The article presents an end-to-end testbed to demonstrate the effectiveness of the proposed Code-Multiplexed Digital Receiver (CMDR) that consists of 1) ultrawideband (UWB) tightly-coupled dipole array (TCDA), 2) a custom-designed encoder circuit board (ECB), and 3) a Radio-Frequency System-on-Chip (RFSoC) field-programmable gate array (FPGA) for encoding and decoding. The code sequences were generated at a maximum clock frequency of 400 MHz. Extensive experimental measurements were performed and test results were validated using performance metrics such as normalized mean square error (NMSE) and adjacent channel interference (ACI). Test results showed ACI of $>$ 20 dB, NMSE = -24.592 dB and little or no degradation in signal-to-noise ratio (SNR). To the best of our knowledge, this is the highest clock frequency and ACI value for hardware validation of channel multiplexing scheme reported in the literature.