利用双栅氧化物提高埋栅场效应管的器件裕度

Youmin Kim
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引用次数: 0

摘要

器件体积缩小和降低非状态功耗是动态随机存取存储器(DRAM)产品开发的关键因素。鉴于市场对高质量器件的需求,由于界面陷阱导致的DRAM单元保持时间的减少和波动,需要一个合适的解决方案来提高产品质量。在本研究中,我们提出了一种器件结构,通过在栅极和漏极的重叠区域实现第二栅极氧化物来降低GIDL电流,并从保持时间的改进中计算其他过程的裕度增量,进行了位线的虚拟a电容/存储帽的a电容(Cb/Cs)评估。该研究有望为陷阱引起的保留时间恶化提供解决方案,并有助于下一代DRAM的开发。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Enhancing Device Margins Using Double-Gate Oxide in Buried-Gat FETs
Abstract Device shrinkage and mitigation of off-state power consumption are crucial factors in dynamic random access memory (DRAM) product development. Given the market demand for high-quality devices, the reduction and fluctuation of DRAM cell retention time, caused by interface traps, required a suitable solution for improved product quality. In this study, we propose a device structure for the reduction of GIDL current by implementing a second gate oxide in the overlapping region of the gate and the drain, and to calculate an increment in the margin for other processes from the retention time improvements, the virtual a capacitance of the bit line/a capacitance of the storage cap(Cb/Cs) evaluation was performed. This study is expected to provide a solution to the trap-induced retention- time deterioration and assist in the development of next-generation DRAM.
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